Crosstalk interferences and high dynamic power consumption in a network-on-chip (NoC) are two increasingly problematic design issues. Using data codecs can reduce the switching activities on wires that cause crosstalk interferences and high dynamic power. However, data codecs have different overheads in terms of area and performance, and varying capabilities in reducing crosstalk and dynamic power. To adapt to the wide range of processing requirements incurred by applications and operating environments, a reasoning and learning (REAL) framework is proposed for a reconfigurable NoC. REAL dynamically investigates the tradeoffs among reliability, dynamic power reduction, performance, and hardware resource usages to configure the reconfigurable NoC with an appropriate data codec at runtime. As a proof of concept, a 3 × 3 reconfigurable NoC was implemented on Xilinx Virtex-4 field-programmable gate array, which required 8.2% lesser number of slices compared with a conventional NoC. Experiments show that at the same overheads of performance and hardware resources the reconfigurable NoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption.

The Fast Fourier Transform (FFT) has been one of the most popular and widely-used transform functions in communication hardware designs. With growing digital convergence, a single device needs to support multiple communication protocols, all of which need FFT computations. Currently, most FFT designs are either not shareable across applications or only among a fixed set of applications. This work proposes a novel reconfigurable FFT design called Spatio-Temporally-shAred Reconfigurable Fast Fourier Transform (STARFFT), which leverages on the partial dynamic reconfiguration technology such that it can be shared across arbitrary set of applications. STARFFT has a software driver that checks feasibility, schedules applications, and reconfigures the hardware. STARFFT hardware has several radix-2 pipelines that are time-multiplexed among applications such that significant reductions in hardware resource requirements and in power consumption are achieved. Experimental results show that STARFFT can reduce the total hardware resource usage by nearly 88% and the power consumption requirements by about 90%.

Communication in a Network-on-Chip (NoC) can be made more efficient by designing faster routers, using larger buffers, larger number of ports and channels, and adaptive routing, all of which incur significant overheads in hardware costs. As a more economic solution, we try to improve communication efficiency without increasing the buffer size. A Buffer-Stealing (BS) mechanism is proposed, which enables the input channels that have insufficient buffer space to utilize at runtime the unused input buffers from other input channels. Implementation results of the proposed BS design for a 64-bit 5-input-buffer router show a reduction of the average packet transmission latency by up to 10.17% and an increase of the average throughput by up to 23.47%, at an overhead of 22% more hardware resources.

The set of applications communicating via a Network-on-Chip (NoC) and the NoC itself both have varying run-time requirements on reliability and power-efficiency. To meet these requirements, we propose a novel Power-aware and Reliable Encoding Schemes Supported reconfigurable Network-on-Chip (PRESSNoC) architecture which allows processing elements, routers, and data encoding methods to be reconfigured at runtime. Further, an intelligent selection of encoding methods is achieved through a REasoning And Learning (REAL) framework at run-time. An instance of PRESSNoC was implemented on a Xilinx Virtex 4 FPGA device, which required 25.5% lesser number of slices compared to a conventional NoC with a full-fledged encoding method. The average benefit to overhead ratio of the proposed architecture is greater than that of a conventional NoC by 71%, 32%, and 277% when we consider the individual effects of interference rate per instruction, application domains, and system characteristics, respectively. Experiments have thus shown that PRESSNoC induces a higher probability toward the reduction of crosstalk interferences and dynamic power consumption, at the same amount of overheads in performance and hardware usage.

With the gradually fading distinction between hardware and software, it is now possible to relocate tasks from a microprocessor to reconfigurable logic and vice versa. However, existing hardware-software scheduling can rarely cope with such runtime task relocation. In this work, we propose a new Relocatable Hardware-Software Scheduling (RHSS) method that not only can be applied to dynamically relocatable hardware-software tasks, but also increases the reconfigurable hardware resource utilization, reduces the reconfigurable hardware resource fragmentation with realistic placement methods, and makes best efforts at meeting the real-time constraints of tasks. The feasibility of the proposed relocatable hardware-software scheduling algorithm was proved by applying it to some randomly generated examples and a real dynamically reconfigurable network security system example. Compared to the quadratic time complexity of the state-of-the-art Adaptive Hardware-Software Allocation (AHSA) method, RHSS is linear in time complexity, and improves the reconfigurable hardware utilization by as much as 117.8%. The scheduling and placement time and the memory usage are also drastically reduced by as much as 89.5% and 96.4%, respectively.

As the number of cores on a chip increases, power consumed by the communication structures takes a significant portion of the overall power budget. In this article, we first propose a circuit-switched interconnection architecture which uses crossroad switches to construct dedicated channels dynamically between any pairs of cores for nonhuge application-specific SoCs. The structure of the crossroad switch is simple, which can be regarded as a NoC-lite router, and we can easily construct a low-power on-chip network with these switches by a system-level design methodology. We also present the design methodology to tailor the proposed interconnection architecture to low-power structures by two proposed optimization schemes with profiled communication characteristics. The first scheme is power-aware topology construction, which can build low-power application-specific interconnection topologies. To further reduce the power consumption, we propose the second optimization scheme to predetermine the operating mode of dual-mode switches in the NoC at runtime. We evaluate several interconnection techniques, and the results show that the proposed architecture is more low-power and high-performance than others under some constraints and scale boundaries. We take multimedia applications as case studies, and experimental results show the power savings of power-aware topology approximate to 49% of the interconnection architecture. The power consumption can be further reduced approximately 25% by applying partially dedicated path mechanism.

NOC architectures have to deliver good latency-throughput performance in the face of very tight power and area budgets. However, the latency and the power consumption for transferring information down the transmitter stack, through the channel, and up the receiver stack might be unacceptably high. In this paper, we evaluate the designs of packet-switched and the proposed circuit-switched NOCs in detail, and we advocate using circuit-switched NOC as it is more attractive for application-specific SOC designs because of communication localization. We implement and synthesize the designs of packet-switched and circuit-switched NOCs, and we take multimedia applications as our case studies. The experimental results show that the area, latency and the energy consumption of packet-switched NOC are much larger than that of circuit-switched NOC.

As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. We first propose a novel 2D segmented interconnect architecture, which uses crossroad switches to dynamically construct a dedicated communication path between any two cores. We then present two application-specific bus operation schemes (normal mode and lease line mode). Each switch may operate with a "lease line", which can dynamically offer a dedicated path between two highly-communicative cores for a specific period according to the application characteristics. Finally, we present a concept of wrappers to help designers use our crossroad architecture as communication backbone. We take the JPEG and MPEG4 reference codes as our case studies and experimental results show the power consumptions can be saved if we dynamically control NoC switches when the behavior of the embedded software is well-known.

As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the SoCs will be heterogeneous in nature with widely varying functionality and communication requirements. The communication topology should possibly match communication workflows among these components. In this paper, the authors first proposed an interconnection architecture for SoC, which uses crossroad switches to construct a dedicated communication path dynamically between any two cores. Then a design methodology for constructing network on chip (NoC) was presented for application-specific computer systems with profiled communication characteristics. A core placement tool, which automatically maps cores to a communication topology such that the total communication energy can be minimized, was proposed. Experimental results show that the design methodology can generate optimized on-chip networks with fewer resources than meshes and tori, and the power saving approximates to 40%.