Iterative Stencil Loops (ISLs) are the key kernel within a range of compute-intensive applications. To accelerate ISLs with Field Programmable Gate Arrays, it is critical to exploit parallelism (1) among elements within the same iteration and (2) across loop iterations. We propose a novel ISL acceleration scheme called Direct Computation of Multiple Iterations (DCMI) that improves upon prior work by pre-computing the effective stencil coefficients after a number of iterations at design time—resulting in accelerators that use minimal on-chip memory and avoid redundant computation. This enables DCMI to improve throughput by up to 7.7× compared to the state-of-the-art cone-based architecture.

Cross language plagiarism is the unacknowledged reuse of text across language pairs. It occurs if a passage of text is translated from source language to target language and no proper citation is provided. Although various methods have been developed for detection of cross language plagiarism, less attention has been paid to measure and compare their performance, especially when tackling with different types of paraphrasing through translation. In this paper, we investigate various approaches to cross language plagiarism detection. Moreover, we present a novel approach to cross language plagiarism detection using word embedding methods and explore its performance against other state-of-the-art plagiarism detection algorithms. In order to evaluate the methods, we have constructed an English-Persian bilingual plagiarism detection corpus (referred to as HAMTA-CL) comprised of seven types of obfuscation. The results show that the word embedding approach outperforms the other approaches with respect to recall when encountering heavily paraphrased passages. On the other hand, translation based approach performs well when the precision is the main consideration of the cross language plagiarism detection system.

Task mapping exploration plays an important role in the high performance achieved by heterogeneous multi-processor system-on-chip (MPSoC) platforms. The dynamic of application workloads in modern MPSoC-based embedded systems are consistently growing. Nowadays, the execution of different applications is done concurrently and these applications compete for resources in such systems. This paper presents a novel run-time mapping algorithm for multimedia applications. The objective of application mapping is to minimize execution time in a predefined budget of energy consumption. This algorithm is divided to two phases: design-time and run-time. During design-time, application clustering is combined with design space exploration, then a set of rules for mapping is extracted by using Association Rule Mining techniques, and after that, during run-time, feature extraction and application classification is performed based on the rule sets. The evaluation of the proposed algorithm is done by using a heterogeneous MPSoC system with several applications that have different communication and computation behaviors. The experimental results revealed that during run-time, applications were correctly classified by the proposed algorithm and the best resources selected for mapping accurately. The results clearly showcase the proposed algorithm's effectiveness.

In multiview video applications, view synthesis is a computationally intensive task that needs to be done correctly and efficiently in order to deliver a seamless user experience. In order to provide fast and efficient view synthesis, in this paper, we present a cloud-based implementation that will be especially beneficial to mobile users whose devices may not be powerful enough for high quality view synthesis. Our proposed implementation balances the view synthesis algorithm's components across multiple threads and utilizes the computational capacity of modern CPUs for faster and higher quality view synthesis. For arbitrary view generation, we utilize the depth map of the scene from the cameras' viewpoint and estimate the depth information conceived from the virtual camera. The estimated depth is then used in a backward direction to warp the cameras' image onto the virtual view. Finally, we use a depth-aided inpainting strategy for the rendering step to reduce the effect of disocclusion regions (holes) and to paint the missing pixels. For our cloud implementation, we employed an automatic scaling feature to offer elasticity in order to adapt the service load according to the fluctuating user demands. Our performance results using 4 multiview videos over 2 different scenarios show that our proposed system achieves average improvement of around 1.7 times for speedup, 50% and 52% for efficiency and resource utilization, respectively.

Electronic System level design has an important role in the multi-processor embedded system on chip design. Two important steps in this process are evaluation of a single design configuration and design space exploration. In the first part of design process, high-level simple analytical models for application mapping and evaluation are used and modified aiming at accelerating the evaluation of a single design configuration. Using the analytical model the design space is pruned and explored at high speed with low accuracy. In the second part of the design process, two Multi Objective Optimization Algorithms based on Particle Swarm Optimization and Simulated Annealing have been proposed to perform design space exploration of the pruned design space with higher accuracy taking advantages of low-level architectural simulation engines. The results obtained by proposed algorithms will provide the designer more accurate solutions within an acceptable time. Considering the MJPEG application as the case study, each of these methods produces a set of near-optimal points. Simulation results show that the proposed methods can lead to near-optimal design configurations with acceptable accuracy in reasonable time.

Mode decision has a significant effect on the quality and complexity of video coding. It is even more challenging when generating multiple bitstreams with different bitrates (BRs) in, for example, dynamic adaptive streaming for HTTP or transrating systems. Full search and simplified fast search mode decision (MD) methods either suffer from a high computational complexity or have a negative impact on quality. Furthermore, mode selection in conventional approaches strongly depends on the quantization parameter (QP). Hence, modes that have been selected for high BR compression may not be suitable for low BR when transrating a bitstream. In this paper, we propose a rate-distortion (R-D)-optimized criterion for fast MD algorithms. The proposed cost function, when adopted in different fast MD algorithms, not only improves the R-D performance by up to 6.6% in terms of Bjøntegaard delta rate, but also reduces the execution time of the encoder by up to 6.8%. We also show that modes selected by the proposed criterion are less sensitive to changes in BR or QP. As a result, the same modes in an encoded bitstream may be used even after transrating using requantization, resulting in a significant R-D performance improvement of up to 33.3%.

It is often essential for people to consult with others and ask them about their past experience and thoughts when making choices. Exchanging ideas among people has become more meaningful since the extensive growth of information on the World Wide Web (WWW). People have access to tremendous amount of information, but choosing the most relevant information is of high effort. It was when recommender systems came into existence in 1992 in order to assist users in the process of finding the most appropriate information on WWW, and identify sets of items which are likely to be interesting for the users. Recommender systems have used different sources of data in order to identify users' interests. In addition, by growth of social resource sharing like social book marking sites, tagging activities can be considered as explicit knowledge for user and item modeling. Existing recommender systems lack use of external source of information for recommending the most appropriate item. They mainly use the information of their own website, while there is valuable information on the web which could improve the performance of the predictions. In this paper, we use Open Directory Project (ODP) data as external knowledge about web pages in addition to tagging activities of users in a social book marking site. We have designed a content based recommender system which can recommend the most relevant web pages for each user based on the user's profile and gathered information about web pages from ODP as implicit data. We empirically evaluate effect of ODP data on the predictions using Delicious dataset in order to analyze the performance of the proposed method. The results show that our recommender system outperforms when it uses ODP information as external source of data.

The mode decision process has a significant effect on the quality and complexity of a video encoder. The conventional method that fully codes each macro block for different modes results in the best quality performance, but it suffers from high computational complexity. On the other hand, some other methods ignore the residual part and use the prediction data, or adopt early mode selection approaches in order to reduce the computational cost. These approaches have a negative impact on the coding performance. In this paper, we have used a simple model for the residual coding part and proposed a two-piece R-D model for a macro block. Based on this model, we have introduced a mode decision algorithm that reduces the bit-rate by up to 11.62% at the expense of just 0.5% computational overhead.

Discrete wavelet transform (DWT) is increasingly recognized in image/video compression standards, as indicated by its use in JPEG2000. The lifting scheme algorithm is an alternative DWT implementation that has a lower computational complexity. In this paper, a new high performance lifting-based architecture is presented for the 9/7 DWT engine. The proposed architecture has a balanced pipeline and improves both the computational error and hardware complexity for any given working frequency. In the proposed architecture, the constant coefficients are modified by introducing new variables to the conventional lifting structure to minimize hardware cost and computational error, imposed by quantization of coefficients. Simulation results indicate a quality improvement of up to 15 dB when compared to an architecture using the standard coefficients that has the same hardware cost and working frequency. Similarly, the hardware cost is reduced by about 20% when both architectures deliver the same PSNR when operating at the same frequency.

Motion estimation is one of the key tools to achieve a very low bit rate in video coding. The selection of optimum motion vectors (MV) has a significant impact on the quality of the resulted compressed video, in Rate-Distortion (R-D) sense. The established method uses the Lagrange multiplier to optimally select the MV for each block. However, it does not consider the effect of residual coding at the same time with the effect of MVs. In this paper, we have considered the effect of residual coding in motion vector (MV) selection with modeling motion estimation and residual coding as independent processes which results in a new optimization condition. It is based on local optimization, which is the bit allocation between motion estimation and residual coding, and global optimization, which is the bit allocation among different blocks. The proposed motion estimation algorithm results in a PSNR improvement of 0.5 - 3.0 dB when it is used in the H.264 standard with block size of 4 times 4.

Naïve-Bayes and k-NN classifiers are two machine learning approaches for text classification. Rocchio is the classic method for text classification in information retrival. Based on these three approaches and using classifier fusion methods, we propose a novel approach in text classification. Our approach is a supervised method, meaning that the list of categories should be defined and a set of training data should be provided for training the system. In this approach, documents are represented as vectors where each component is associated with a particular word. We propose voting methods and OWA operator and Decision Template method for combining classifiers. Experimental results show that these methods decrese the classification error 15 percent as measured on 2000 training data from 20 newsgroups dataset.

Discrete wavelet transform (DWT) is increasingly recognized in image/video compression standards, as indicated by its use in JPEG2000. The lifting scheme algorithm is an alternative DWT implementation that has a lower computational complexity. In this paper, a new high performance lifting-based architecture with optimized error vs. hardware complexity is presented for DWT. The proposed architecture modifies the constant coefficients by introducing new variables to the conventional lifting structure to minimize hardware cost and quantization error. In order to achieve the most efficient coefficients, an optimization process has been implemented. Simulation results indicate an average quality improvement of 7.5 dB with the same hardware complexity/cost. Similarly, for achieving the same quality as the conventional hardware implementations the proposed architecture is 20% less complex. The appropriate coefficients can be determined according to the cost and error requirements of each application.

Digital image transmission is widely used in consumer products, such as digital cameras and cellular phones, where low bit rate coding is required. In any low bit rate encoder, such as the JPEG2000 standard, data truncation (during the encoding process), and data loss (during transmission) will result in lost bit-planes, which will be normally replaced by zeros. In this paper a new algorithm has been proposed, which recovers the lost/truncated lower bit-planes of coefficients in the LL subband of a wavelet transform in a JPEG2000 stream using the data available in higher bit-planes of the same coefficient and its eight neighbors. Simulation results indicate that the proposed algorithm achieves 5.40-8.77 dB improvement with respect to zero filling data recovery method.

Implementing the discrete wavelet transform, which is being increasingly recognized in image/video compression standards, in hardware is highly area-consuming. In this paper, a new high-performance lifting-based architecture with optimized error vs. hardware cost is proposed for the 9-7 DWT. In the proposed architecture each constant coefficient multiplier of the conventional lifting structure is split into two new constant multipliers in order to minimize the hardware implementation cost and quantization error. Using an optimization process the appropriate coefficients are determined according to the hardware cost and quality requirements of each application. Simulation results indicate an average quality improvement of 13.5 dB with the same hardware resources. For achieving the same quality, it requires 40% less hardware resources, which makes it suitable for embedded systems.

In this paper, a routing model for minimizing hot spots in the network on chip (NOC) is presented. The model makes use of AntNet routing algorithm which is based on Ant colony. Using this algorithm, which we call AntNet routing algorithm, heavy packet traffics are distributed on the chip minimizing the occurrence of hot spots. To evaluate the efficiency of the scheme, the proposed algorithm was compared to the XY, Odd- Even, and DyAD routing models. The simulation results show that in realistic (Transpose) traffic as well as in heavy packet traffic, the proposed model has less average delay and peak power compared to the other routing models. In addition, the maximum temperature in the proposed algorithm is less than those of the other routing algorithms.

One of the main reasons behind the superior efficiency of the H.264/AVC video coding standard is the use of an in-loop deblocking filter. Since the deblocking filter is computation and data intensive, it has a profound impact on the speed degradation of both encoding and decoding processes. In this paper, we propose an efficient deblocking filter architecture that can be used as an IP core either in the dedicated or platform-based H.264/AVC codec systems. Novel self-transposing memory unit is used in this paper to alleviate switching between the horizontal and vertical filtering modes. Moreover, to reduce the processing latency, a two-stage pipelined architecture is designed for 1-D filter that produces output data after 2 clock cycles. With a clock of 100 MHz the proposed design is able to process a 1280times1024 (4:2:0) video at 25 frame/second. The proposed architecture offers 33% to 56% performance improvement compared to the existing state-of-the-art architectures

R-D optimization algorithm is frequently used where subband coding or vector quantization is required. All existing R-D optimization algorithms have an iterative process which results in more computational complexity and execution time. In this paper we propose a novel R-D optimization algorithm that has a non-iterative process with lower computational complexity. This algorithm is based on exponential modeling of R-D curves and can be used in rate-constraint problems. The proposed algorithm presents a good performance with non-convex curves as well as convex ones. While the execution time of the existing algorithms is O(Ncrv×Npt), the execution time of the proposed algorithm is O(Ncrv), where Ncrvis the number of curves and Nptis the average number of points in each curve. The quality degradation is 0.32 dB, in average, when it is tested in the rate control component of a JPEG2000 encoder.

The order and arrangement of the main components in a JPEG2000 encoder, referred to as coding sequence hereafter, plays a significant role in its performance and implementation cost. Typical JPEG2000 encoders, which may use a pre-compression or a post-compression bit allocation, require a large amount of memory to store the wavelet coefficients, compressed data and R-D curves. In this paper, we propose a novel coding sequence with a pre-compression bit-allocation method that requires just a small portion of data in order to generate the final bit-stream. The proposed method is based on multi-layer coding and can be used in distortion-constrained applications of JPEG2000. Using this coding sequence, the memory requirements of a JPEG2000 system is reduced more than 50% while the quality degradation is only 0.4 dB in average.

The MISP processor is a programmable media processor which supports multi-issuing, multi-threading and stream processing techniques. MISP executes applications that have been mapped to the stream programming model. The stream model decomposes applications into a set of computation kernels that operate on data streams. This mapping exposes the inherent locality and parallelisms in media applications. MISP exploits thread level (TLP), data level (DLP), sub-word (SP) and instruction level (ILP) parallelisms inherent in media applications. Full simulator of MISP has been implemented and several media workloads composed of EEMBC benchmarks have been applied. Also we applied test programs on imagine stream processor. The simulation results show MISP gains IPC of more than 2.08 times and performance of more than 1.86 times over imagine. The synthesis results show area overhead per thread addition in MISP is about 7% without changing clock frequency

In multimedia applications where images are extremely used, the rate control method has a significant role in image encoder performance, computational complexity and hardware implementation. We propose a simple rate control algorithm suitable for the hardware implementation of a JPEG2000 encoder with less computational complexity and area. The proposed algorithm, which is based on exponential modeling of R-D curves, employs distortion instead of slope values. Simulation results show similar performance compared to the full search method, with considerable reduction in hardware resources.

The advances in VLSI technology, high-speed processor designs, Internet/Intranet implementations, broadband networks (ATM and ISDN), and compression standards (JPEG, MPEG, H.261, H.263, and G.273) are leading to the popularity of multimedia applications. Examples include video over the Internet, interactive TV, distance learning, telemedicine, and digital libraries. Visual media processing poses challenges from several perspectives, specifically from the points of view of real-time implementation and scalability. We first present an overview and categorization of the various architectural approaches for multimedia processing. The fundamental operations involved in a majority of visual processing tasks are then derived. We propose an affine transform-processor-core-based video processor architecture called the fractal engine that is capable of implementing the basic visual processing operations. The fractal engine is an open architecture, and is designed to be modular and scalable, and therefore has the potential to satisfy the heterogeneous computing requirements of the different media types in multimedia processing. Details of the individual modules of the fractal engine as well the implementation of the architecture in VHDL are also presented.

The main objective of this paper is to design a Persian text recognition system. As even typed Persian scripts are cursive, our system includes a segmentation stage in order to separate the constituent characters. This stage is also useful for highly declined or italic Latin texts. A new segmentation algorithm with two consecutive steps is introduced in this paper. The first step separates isolated and non overlapped characters as well as some overlapped ones. The second step segments not connected overlapped characters. The novel segmentation method has been tested on some real world script and has shown an accuracy rate of more than 99.7%. In the recognition stage which involves a statistical approach, two types of feature sets along with different classification methods are evaluated.