Yield improvement, yield ramp, and defect screening have been major areas of concern for the semiconductor industry as technology nodes have advanced. Much effort has been focused on capturing the defects missed by traditional stuck-at and transition delay fault model based testing. A majority of these un-modeled defects stems from features inside a standard cell or between two adjacent standard cells. Traditionally, critical area has been used as the manufacturability guideline to determine opens and shorts that should be targeted for test. This paper motivates a new paradigm - a design-for-manufacturability (DFM) hotspot-aware fault model to target intra-cell and inter-cell defects. The basic objective behind this approach is to bring in knowledge of manufacturing vulnerability in design layouts to weigh likelihood of occurrence of systematic defects. Recent technologies have standard cells much smaller than the lithography-driven optical diameter which means the cell's feature context is a key driver for DFM-driven fault sensitivity. This paper describes a novel automated flow for cell characterization that can be used to create patterns at the cell boundary for DFM-aware faults. The paper presents ATPG results for different DFM-aware faults, and analyzes the coverage gaps. Finally, the paper ends with a comparison with the cell-aware and dual-cell-aware fault models, and describes relative advantages and application scenarios.

This session is organized as part of the activities sponsored by IEEE Test Technology Technical Council (TTTC) Young Professionals Forum. The primary goal of this forum is to align the young professionals, both from industry and academia, working in the broad domain of manufacturing test and applications, with the activities of TTTC. This forum was initiated in 2013 and had its first meetings at VLSI Test Symposium (VTS) and International Test Conference (ITC) of that year. This year we are expanding our presence in the VTS by introducing a new session showcasing the research conducted by the young colleagues from industry and academia. The Elevator Talk session includes presentations on “Malicious Aging Acceleration in Processors” by Naghmeh Karimi from New York Polytechnic University, “RF Built-In Test with Non-intrusive Sensors” by Haralampos Stratigopoulos from TIMA Laboratory, France, “Advanced Process Bring-up” by Sounil Biswas from nVidia, “Exploration of Vector-based Integer Arithmetic on Intel Xeon Processors” by Michail Maniatakos from New York University, Abu Dhabi and “Detecting Hardware Trojans with Self-Reference Timing Tests” by Eshan Singh from Intel Corporation. Through this Elevator Talk session, we encourage a broader section of young colleagues to participate in the similar session of future meetings.

In the year 2013, IEEE Test Technology Technical Council (TTTC) took an initiative to establish a forum involving young professionals (both from industry and academia) working in the broad domain of manufacturing test, diagnosis, debug, yield improvement and related areas. We organized panel meetings in conjunction with VLSI Test Symposium (VTS) and International Test Conference (ITC) last year to focus on the professional needs identified by the young colleagues that TTTC can help address. This is the third successive meeting of this forum that involves a diversified group of young professionals currently employed in the leading US semiconductor/EDA companies and in academia. The session will be held in town-hall format, organized by Dr. Alodeep Sanyal from Intel, and moderated by Dr. Yervant Zorian from Synopsys. The panelists will be involved in defining the charter for this newly-formed TTTC forum and establish a committee that will actively engage in monitoring these activities. Few of the focus areas include: (a) Create and maintain a webpage for Young Professionals (YP) Forum linked with the TTTC webpage, (b) Establish and nurture professional collaboration between young colleagues in academia and industry, (c) Create and maintain an employment opportunity database for graduating students. We invite everybody to attend the panel and voice their opinion from the audience.

IEEE Test Technology Technical Council (TTTC) takes an initiative to establish a forum involving young professionals working in the broad domain of test, diagnosis, yield improvement and related areas. We have formed a panel involving a diversified group of young professionals (recent PhD graduates from US and Canadian universities) currently employed in the leading US semiconductor and EDA companies. The session will be held in town-hall format, organized by Dr. Alodeep Sanyal from Synopsys and Dr. Yanjing Lin from Intel, and moderated by Dr. Yervant Zorian from Synopsys. The panelists will be involved in discussing the objectives of this newly-formed TTTC forum and the activities it should monitor. Some of the topics of discussion may include: (a) The benefits that TTTC can offer to the young professionals; (b) Establishing a connection between working professionals and graduate students that may provide research/mentoring opportunities for the professionals; (c) An actively maintained job requisition database exclusively available under TTTC for the student members to help them apply for a suitable job. The overall topic of discussion for this panel has been left quite open-ended for participants to propose their own ideas. We expect this panel will identify the future direction and activities for the TTTC Young Professionals Forum.

Computation of peak supply current is central to power rail design and analysis of power supply switching noise. Traditionally, peak switching current from all CMOS gates is added together to compute peak supply current. This approach can be improved significantly if temporal and Boolean relationships are taken into consideration. Previously, it was shown that worst case switching current in a subset of gates may imply that some other gates may not have the worst case switching condition due to logical relationship between input patterns of a gate. In this paper, we also take integer gate delays into consideration to show that gate switching events may be spaced out in time leading to lower peak current. Further, it is found that taking gate delays into account actually simplifies the size of individual problem instances to be solved, leading to both a faster and more accurate solution. Finally, we compare peak current waveform generated by the proposed solver against SPICE simulation to demonstrate effectiveness of the proposed solution.

Decreasing process geometries and increasing operating frequencies have made VLSI circuits more susceptible to signal integrity related failures. Capacitive crosstalk on long signal nets is of particular concern. A typical long net is capacitively coupled with multiple aggressors and also tend to have multiple fan-outs. Gate leakage current that originates in fan-out receivers, terminates in the driver causing a shift in driver output voltage. This effect becomes more prominent as gate oxide is scaled more aggressively. Thus, in nano-scale CMOS circuits, noise margin gets eroded by both aggressor crosstalk noise as well as gate leakage loading from fan-outs. In this paper, we present an automatic test pattern generation solution which uses 0-1 integer linear programming to maximize the cumulative voltage noise at a given victim net because of crosstalk and loading in conjunction with propagating the fault effect to an observation point. The target ISCAS benchmark circuits are assumed to have unit gate delays. Results demonstrate both the viability of a solution as well as a need to consider both sources of noise for signal integrity analysis. Pattern pairs generated by this technique are useful for both manufacturing test application as well as signal integrity verification.

Functional test sequences play an important role in manufacturing test for targeting defects that are not detected by structural test. In practice, functional tests are often derived from existing design-verification test sequences and they suffer from low defect coverage. Therefore, there is a need to increase their effectiveness using design-for-testability (DFT) techniques. We present a non-scan DFT technique at the register-transfer (RT) level that tackles the above problem in three steps. It can be used to increase the defect coverage for scan-based designs by making functional test sequences more effective in native (non-scan) mode. The proposed method selects a small set of control points, and through an efficient branch-and-bound strategy, determines an effective set of truth assignments to these control points (also called test modes). The original functional test is expanded by applying the same functional test sequence once with each selected test mode. Finally, a small set of state elements are chosen as observation points from the transitive fanout cone of the control points based on the number of recorded transitions. The proposed DFT method is evaluated in terms of the unmodeled defect coverage, and we introduce a new surrogate metric, called multi-segment long path sensitization, for the purpose of evaluation. Experimental results for the ITC'99 benchmark circuits, the Open RISC 1200 SoC benchmark, and the Scheduler module of the Illinois Verilog Model (IVM) show that the proposed non-scan DFT technique offers significant potential for ramping up the defect coverage of existing functional test sequences.

With the scaling of CMOS technology, subthreshold, gate, and reverse biased junction band-to-band-tunneling leakage have increased dramatically. Together, they account for more than 25 percent of power consumption in the current generation of leading edge designs. Different sources of leakage can affect each other by interacting through resultant intermediate node voltages. This is called the loading effect. In this paper, we propose a pattern dependent steady-state leakage estimation technique that incorporates loading effect and accounts for all three major leakage components, namely the gate, band-to-band-tunneling, and subthreshold leakage and accounts for transistor stack effect. By observing a recursive relationship between gate leakage and loading effect, we further refine our leakage estimation technique by developing a compact leakage model that supports iteration over node voltages based on Newton-Raphson method. The proposed estimation technique based on the compact model improves performance and capacity over SPICE. We report a speedup of 18,000X over SPICE simulation on smaller circuits, where SPICE simulation is feasible. Results also show that loading effect is a significant factor in leakage and worsens with technology scaling.

Capacitive crosstalk induced signal integrity effects have been studied for over a decade. A typical victim net has multiple aggressors. In worst-case analysis of crosstalk effects, it is customary to assume that (i) all aggressors can switch at the same time and (ii) aggressors themselves are not subject to other crosstalk effects. Further refinements of the worst-case analysis consider (a) Boolean filtering of the aggressors to take logical relationship among them into account and (b) timing filtering to exclude aggressors that cannot switch in the same timing window where the victim node is switching. However, even further refinement is possible by relaxing supposition (ii) above that assumes that aggressors are not subject to noise themselves. In this paper, we present a simulation study that considers multiple crosstalk effects where the aggressors of one net can be victim themselves with signals switching in their neighborhood. The simulations are performed on an innovative compact model that permits circular reasoning in an event-driven, non-zero gate delay, and dynamic simulation framework. Results indicate that when crosstalk on aggressors is also considered while processing crosstalk on a victim, the impact is often mitigated substantially.

Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies, and the trend is expected to get worse. The measurement unit for failures due to soft errors is failure in time (FIT) that represents the number of failures encountered per billion hours of device operation. FIT rate measurement is time consuming and calls for accelerated testing. To improve effectiveness of soft-error rate (SER) testing, the patterns must be targeted toward detecting node failures that are most likely. In this paper, we present a technique for identifying soft-error-susceptible sites based on efficient electrical analysis that treats soft errors as Boolean errors but uses analog strengths to decide whether such errors can propagate to the next stage. Next, we present pattern generation techniques for manifestable soft errors such that each pattern targets a maximal set of soft errors. These patterns maximize the likelihood of detecting a soft error when it occurs. The pattern generators target scan architecture. It is well known that scan test time is dominated by scan shifts, when no useful testing is being done. To improve efficiency of scan-based testing, we extend the functionality of the existing built-in logic block observation (BILBO) architecture to support test-per-clock operation. Such targeted pattern generation and test application improve SER characterization time by an order of magnitude.

Scaling of transistor feature size over time has been facilitated by corresponding improvement in lithography technology. However, in recent times the wavelength of the optical light source used for photolithography has not scaled in the same rate as that of the minimum feature size of the transistor. In fact, starting with 180 nm devices, the wavelength of optical source has remained the same (at 193 nm) due to difficulties in finding a flicker-free, high energy, coherent light source with compatible improvement in lens material for focusing this light. Consequently, upcoming technology nodes (65 nm, 45 nm, 32 nm and 22 nm) will be using a light source with wavelength much greater than the feature size. This creates a peculiar problem where line width on manufactured devices is a function of relative spacing between adjacent lines. Despite numerous restriction on layout rules, interconnects may still suffer from constriction due to this peculiarity also known as forbidden pitch problem. A small manufacturing variation turns the constrictions to open faults. Gate leakage current is a significant concern for present and upcoming technology nodes. Due to gate leakage, an open fault is not truly an open circuit. Our simulation studies show that the leakage current steers the floating input of a gate to certain meta- stable states. This property actually makes it easier to detect open faults either through side channel excitation or by stuck-at tests. The major contributions of this paper are (i) lithographic simulation based identification of potential open fault sites, (ii) identification of meta-stable input states for these open inputs, (iii) length calculation for side channel signals for definitive detection of open faults. Together, they provide a complete CAD framework for testing lithography related open faults.

Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. Soft error rate (SER) measurement, expressed as number of failures encountered per billion hours of device operation, is time consuming and involves significant test cost. The cost stems from having to connect a device-under-test to a tester for extended period of time. While built-in self-test (BIST) mechanisms have been around for over a decade, that minimizes the use of a tester; they have not been applied to measure or characterize soft error rate. This is because traditional BIST methods cannot distinguish between a soft failure and a hard failure and have no provision for counting the number of errors. In this paper, we propose a BIST design for soft error rate (SER) characterization, which obviates those issues. The proposed BIST based SER measurement scheme can be further accelerated by improved controllability and observability while unlike traditional BIST schemes, a test by test failure detection capability enables higher diagnostic resolution for single event based transient errors. We further propose to integrate this chip-level BIST-based SER characterization system with a distributed on-line scheme using a network controller that tests multiple chips in parallel and completely eliminates the need for a tester. The hardware overhead of the proposed architecture is small and it becomes insignificant for larger design.

In this paper we propose a technique for increasing the rate of failure due to soft errors by carefully choosing the patterns for soft-error detection. It is well known that all circuit nodes are not equally vulnerable to soft error. We propose a metric for measuring vulnerability of a node to soft-error. The pattern selection approach constructs a test set to maximize the node vulnerability metric. In order to facilitate scan based application of these tests, we propose a test-per-clock DFT scheme that allows counting of such errors. The test set thus derived is applied repeatedly to accelerate the soft error rate measurement. Acceleration reported for this technique over random pattern testing on ISCAS-85 benchmarks ranges from 5X to infinity.

Soft errors caused by ionizing radiation have emerged as a major concern for current generation of CMOS technologies and the trend is expected to get worse. A significant fraction of soft errors in semiconductor has been reported to never lead to a system failure. System level soft-error rate (SER) analysis shows that soft-error in internal circuit nodes frequently fail to propagate to an observable point due to Boolean filtering and latching window filtering. A previous study shows that when soft-error is viewed as an analog signal distortion rather than a digital error, it often disappears during signal propagation due to error signal attenuation. This has been termed as electrical filtering. Electrical filtering in system level soft-error rate analysis is expensive because it involves circuit level simulation. In this paper, we present an electrical filtering technique that treats soft-errors as digital errors, but uses analog strengths to decide whether such errors can propagate. We call this techniquestrengthfiltering. Strength filtering does not involve SPICE simulation, hence it is computationally efficient. Used as a pre-processing step, strength filtering improves the efficiency of system level soft-error rate analysis. Experimental results on ISCAS-85 benchmark circuits show that an average of ~38% of the soft errors have no potential impact on the system level behavior and therefore, can be filtered out to improve both accuracy and efficiency of soft rate estimation process.

Max-current analysis is essential in power rail design and power supply switching noise analysis. Traditionally, maximum current from all CMOS gates are added together to compute maximum current level. This approach ignores all Boolean relationships. The problem of finding the input vector pair that will cause worst case current draw from the power rails when Boolean relationships are considered is an NP-hard problem. In this paper, we propose a Current Maximizing Pattern Generation (CMPG) algorithm which greatly reduces the computational complexity by using a parameterized branch-and-bound heuristic that prunes the search space by looking for a lower as well as an upper bound for maximum switching currents. When allowed to proceed indefinitely, the CMPG algorithm converges on an exact solution instead of finding upper and lower bounds. When coupled with a switch level SAT solver, CMPG can generate patterns for cell library characterization.

Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume significant dynamic power during testing because of enhanced switching activity in the internal nodes. Our work focuses on the fact that power minimization is a traveling salesman problem (TSP). We explore application of local search and genetic algorithms to test set reordering and perform a quantitative comparison to previously used deterministic techniques. We also consider reduction of the original test set as a dual-objective optimization problem, where switching activity and fault coverage are the two objective functions.