In this paper we address the growing issue of gate oxide leakage current (I gate) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both I gate and subthreshold leakage (I sub). The interaction between I sub and I gate complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on table look-ups to quickly estimate the state-dependent total leakage current within 1 % of SPICE. We then make several observations on the impact of I gate in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR vs. NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce I gate due to the dependence of gate leakage on stack node voltages.