Second-life lithium-ion batteries retrieved from electric vehicles are a very appealing resource for stationary applications such as smart grids. However, their performance is limited by the strong mismatch among their cells. Dynamic equalization is a very promising approach to maximize the second-life battery capacity, transferring charge from the best-performing cells to the least-performing ones. Even if this functionality is very similar to the active balancing approach used in first-life batteries, the dynamic equalization approach requires high-current DC/DC converters. Therefore, converter design is crucial for obtaining high efficiency in all possible battery states. A novel approach to determine in closed form the efficiency of a super-capacitor-based active balancing architecture was developed. It can estimate the efficiency of the system with comparable accuracy, but in a significantly shorter time than other methods presented in the literature. Such considerable advantages make the proposed approach a valuable tool for implementing optimization procedures, thus helping the designer in the selection of the components for the design of the active balancing circuit considered.

Sodium-ion batteries offer a promising alternative to lithium-ion ones thanks to their lower cost, smaller ecological footprint, and less stringent safety requirements. The development of an accurate model to reproduce their behaviors is still an open issue, despite being essential for enabling their efficient utilization. This work investigates the repurposing of lithiumion equivalent circuit models for sodium-ion cells. Four models with 1, 2, 3, and 4 RC groups are considered to investigate their trade-off between accuracy and computational efficiency. The model parameters are identified with a pulse current test carried out on two nominally identical commercial cells. The performance of the models is evaluated using pulse current tests and a realistic electric vehicle current profile. In both cases, all the models achieve errors lower than 1% of the nominal cell voltage. These values are comparable with those obtained in lithium-ion cell models, suggesting the portability of model-based algorithms from lithium-ion batteries to sodium-ion ones. Moreover, the results highlight that the model with 2 RC groups is the best choice in low computational complexity systems. On the other hand, the model with 3 RC groups has the best trade-off between accuracy and computational complexity.

FPGAs are a hardware solution for applications that require low power usage and real time execution. This work focuses on motor control. We show the design and FPGA implementation of a motor controller based on a small Neural Network (NN) as alternative to a traditional Proportional Integral (PI) controller that was used as reference. Performance metrics are defined from a simulation of the target motor. We investigate different NNs, training, code generation methods and numerical precisions. The best-performing controller is a multilayer NN trained with Reinforced Learning. The controller is implemented and runs on an Intel MAX 10 FPGA. The methodology described in this work is easily applicable to more complex designs when FPGAs become the best implementation platform.

This paper aims at presenting new solutions for advanced Li-Ion battery management to meet the performance, cost and safety requirements of automotive applications. Emphasis is given to monitoring and controlling the battery temperature, a parameter which dramatically affects the performance, lifetime, and safety of Li-Ion batteries. In addition to this, an innovative battery management architecture is introduced to facilitate the development and integration of advanced battery control algorithms. It exploits the concept of smart cells combined with an FPGA-based centralized unit. The effectiveness of the proposed solutions is shown through hardware-in-the-loop simulations and experimental results.

This paper discusses the hardware implementation and experimental validation of a model-based battery state estimator. The model parameters are identified online using the moving window least squares method. The estimator is implemented in a field programmable gate array device as a hardware block, which interacts with the embedded processor to form a system on a chip battery management system (BMS). As a case study, the BMS is applied to the battery pack of an e-bike. Road tests show that the implemented estimator may provide very good performance in terms of maximum and rms estimation errors. This work also proposes a new methodology to assess the performance of a battery state estimator.

A Battery Management System (BMS) is needed to ensure a safe and effective operation of a Lithium-ion battery, especially in electric vehicle applications. An important function of a BMS is the reliable estimation of the battery state in a wide range of operating conditions. To this end, a BMS often uses an equivalent electrical model of the battery. Such a model is computationally affordable and can reproduce the battery behaviour in an accurate way, assuming that the model parameters are updated with the actual operating condition of the battery, namely its state-of-charge, temperature and ageing state. This paper compares the performance of two battery state and parameter estimation techniques, i.e., the Extended Kalman Filter and the classic Least Squares method in combination with the Mix algorithm. Compared to previous ones, this work focuses on the concurrent estimation of battery state and parameters using experimental data, measured on a Lithium-ion cell subject to a current profile significant for an electric vehicle application.

This paper shows an effective implementation of the fast charging concept in the electric local public transport context. An electric minibus powered with a lead-acid battery is considered as a case-study. Its traction battery is redesigned using 12 V standard lithium-iron-phosphate modules to benefit from the higher performance of the lithium battery technology compared to the lead-acid one. The minibus can achieve a continuous operation characterised by 20 min of traveling alternated with 10 min of standstill for fast recharging of the battery. Experiments performed on a single module of the battery show that the load profile is sustained without appreciable issues both in temperature and life degradation of the lithium cells.

The hysteresis in the state-of-charge (SoC) vs. open-circuit voltage characteristic of a lithium-iron-phosphate (LiFePO4, LFP) battery is modelled with two approaches. The first one is based on a first-order charge relaxation equation, the second one is the Preisach model implemented with the Everett function. The advantages and drawbacks of the methods are discussed. Simulation results are compared for a 20 A h LFP cell, stimulated with various SoC evolutions, allowing us to draw minor loops in the SoC-OCV plane. The results are also compared to experimental data.

This paper describes the hardware implementation of a model-based State-of-Charge (SoC) estimation algorithm for Lithium-ion batteries. SoC estimation is essential to evaluate the remaining runtime of the battery, as well as to enhance its safety and life expectancy. Model-based SoC estimation is a good solution to the problem, but only offline tests have been presented so far. In this work, the SoC estimation algorithm is implemented on an FPGA device, following an innovative and automatic development flow, which starts from a MATLAB/Simulink model of the algorithm. The SoC estimation hardware block is combined with a soft-core processor to form a System on a Programmable Chip. Experimental results obtained exerting the battery with a current profile that simulates its operation in an electric vehicle are presented and discussed.

This paper presents a novel charge equalization technique seamlessly integrated into a modular Battery Management System (BMS) for lithium-ion (Li-ion) batteries. The charge equalizer is a crucial element for an effective use of a Li-ion battery consisting of many series-connected cells. We describe a fully distributed charge equalizer based on a circular balancing bus, which outperforms other recently published approaches. Its safety requirements have formally been verified using a model checker, showing that formal methods and, in particular, the Symbolic Analysis Laboratory environment, can be effective to verify the safety requirements of a BMS.

Lithium-ion batteries are increasingly being used in safety-critical applications, such as automotive, avionics and aerospace systems. They require the adoption of an electronic control system, called Battery Management System (BMS), to guarantee their safe and effective operation. Therefore, the reliability of the BMS is of paramount importance. In this paper, we analyze the effects of Single Event Upsets (SEUs) occurring in the control logic of an important BMS subsystem, i.e., the charge equalizer. Moreover, some SEU mitigation techniques based on logic redundancy are presented and their effectiveness is compared through fault simulation.

This paper aims at investigating and modelling the hysteresis in the relationship between state-of-charge and open-circuit voltage of lithium-iron-phosphate batteries. A first-order charge relaxation equation was used to describe the hysteresis dynamics. This equation was translated into a voltage-controlled voltage source and included within an equivalent electric circuit of the battery used in online state-of-charge estimators. The effectiveness of the obtained battery model was verified comparing simulated and experimental data.

The charge stored in series-connected lithium batteries needs to be well equalized between the elements of the series. We present here an innovative lithium-battery cell-to-cell active equalizer capable of moving charge between series-connected cells using a super-capacitor as an energy tank. The system temporarily stores the charge drawn from a cell in the super-capacitor, then the charge is moved into another cell without wasting energy as it happens in passive equalization. The architecture of the system which employs a digitally-controlled switching converter is compared with the state of the art, then fully investigated, together with the methodology used in its design. The performance of the system is described by presenting and discussing the experimental results of laboratory tests. The most innovative and attractive aspect of the proposed system is its very high efficiency, which is over 90%.

The battery is a fundamental component of electric vehicles, which represent a step forward towards sustainable mobility. Lithium chemistry is now acknowledged as the technology of choice for energy storage in electric vehicles. However, several research points are still open. They include the best choice of the cell materials and the development of electronic circuits and algorithms for a more effective battery utilization. This paper initially reviews the most interesting modeling approaches for predicting the battery performance and discusses the demanding requirements and standards that apply to ICs and systems for battery management. Then, a general and flexible architecture for battery management implementation and the main techniques for state-of-charge estimation and charge balancing are reported. Finally, we describe the design and implementation of an innovative BMS, which incorporates an almost fully-integrated active charge equalizer.

The architecture of a hierarchical Battery Management System is presented focusing on the design of its hardware building blocks. The system is intended to be used in a fuel-cell powered van and the design is optimized for large lithium battery packs. The developed BMS provides monitoring and protection functions, together with a high efficiency cell equalization circuit that can selectively adjust the State of Charge of each cell of the pack. A preliminary experimental validation of some building blocks is presented and measurement results are discussed.

This paper presents a low-cost and simple distributed force sensor that is particularly suitable for measuring grip force and hand position on a steering wheel. The sensor can be used in automotive active safety systems that aim at detecting driver's fatigue, which is a major issue to prevent road accidents. The key point of our approach is to design a chain of sensor units, each of them provided with some intelligence and general purpose capabilities, so that it can serve as platform for integrating different kinds of sensors into the steering wheel. A proof-of-concept demonstration of the distributed sensor consisting of 16 units based on capacitive sensing elements has been realised and preliminary results are presented.

In this paper we present a high-performance configurable multi-channel counter, suitable for many scientific applications. The counter array features 64 input channels, is able to acquire incoming events with a pulse rate up to 45 MHz, and provides an integration window (time resolution) down to 24 mus with a 32 b counting depth. Moreover, the time resolution reaches the value of 8 mus with a 8b counting depth and 1 mus if only 8 channels are used. The collected data are both real-time processed and transmitted over a high-speed IEEE 1394 serial link. The same link is used to remotely set up and control the entire acquisition process, thus giving the system a high degree of flexibility. A small-sized and low-cost implementation is obtained with a Commercial-Off-The-Shelf FPGA/DSP-based single board. A theoretical model that immediately gives the system performance is presented. Finally, we describe the system functional test, the results of which are in good accordance with those derived from the model.

This paper describes a hardware-software platform suitable for rapid prototyping of electronic systems for in-motorcycle applications. The hardware platform architecture is characterized by two programmable components consisting of an 8-bit microcontroller and a PC-like device, such as a portable PC or a PDA, which communicate by means of a Bluetooth wireless link or a CAN bus. The application can dynamically be partitioned on the two processors, during the design and verification phases. This allows the hardware-in- the-loop simulation and the fine-tuning of the control algorithm before porting the application to the embedded processor. Two application examples for motorcycles are presented. They demonstrate that the designed hardware/software platform leads to rapid and low-cost implementations of innovative in- motorcycle electronic systems.

At-speed scan testing is becoming more and more popular in the semiconductor industry, as the relevance of delay-induced defects increases with CMOS process scaling and consequent IC complexity growth. This paper reports an industrial experience that demonstrate that at-speed transition fault testing is a crucial manufacturing step also for designs fabricated in mature processes and characterized by rather low working frequency, at least for highly reliable applications, such as automotive electronics and avionics. We present the identification of a timing- related defect on faulty parts and we discuss the application of at-speed scan testing which allowed us to achieve zero ppm final defect level after tests. The design was a serial communication receiver featuring an internal RC oscillator with 15 MHz typical oscillating frequency, fabricated in 0.8 mum CMOS technology.

In this work we describe the realization of a wireless audio communication system that makes available to the driver and the passenger of a motorcycle a wide range of attractive audio services such as an intercom, listening to FM radio or navigational messages from a GPS navigator, placing phone calls by means of a cellular phone. The novelty and the key point of this wireless system is the multi-point Bluetooth audio network formed and managed by the audio communication unit placed on the vehicle. This unit acts as an audio access-point to which the users, equipped with standard Bluetooth headsets, independently connect, register and access the available audio services. The demonstrator realized is also described to show that the proposed system efficiently provides significant and new infotainment features to the motorcycle riders

This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were designed in a 0.6-/spl mu/m CMOS technology and verified. Post-layout simulations show that semi-custom adiabatic arithmetic units can save energy a factor 17 at 10 MHz and about 7 at 100 MHz, as compared to a logically equivalent static CMOS implementation. The energy saving obtained is also better if compared to other custom adiabatic circuit realizations and maintains high values (3/spl divide/6) even when the losses in power-clock generation are considered.

This paper presents a customizable injection fault system and performance evaluations of dependable memory collars designed by GRAAL tool. The novelty consists in a large number of tests and architecture comparisons which can demonstrate the efficiency and validity of GRAAL and how it helps the designer to experiment the architecture sensitivity and evaluate changes in performances when a particular dependable memory collar is chosen or bypassed. Moreover, a complete test set-tip and real case study where the memory interacts in a complex system is described The system collects information to measure the effects of fault detection and fault tolerance. The hardware is assembled in a configurable test board with a FPGA where are one of several memory wrapper which GRAAL generates and a serial link to receive and send data from an acquisition system. Two commercial Personal Computers interact thought the boards and collect data from the experiment.

This paper presents a new architecture for the hardware implementation of additive synthesis for high-quality musical sound generation. A marginally stable second-order infinite-impulse-response filter is used to generate each sinusoid, the frequency, amplitude, and phase of which can independently be specified. a chip has been designed with a bit-level systolic array approach. It is capable of performing 1200 sinusoid real-time synthesis. Furthermore, it is possible to connect up to II chips, to achieve an outstanding 13 200 sinusoid synthesis. Two completely independent output channels are available as 20-b streams. The system is clocked at 60 MHz when working with a 44.1-kHz sampling rate. The integrated circuit is designed in a 0.5-mu m CMOS technology and has a core area of approximately 19 mm(2).

This paper presents a new hardware implementation of additive synthesis for high quality musical sound generation. The single-chip configuration is capable of performing 1,200 sinusoid real-time synthesis; the system is expandable to 13,200 partials by series connecting 11 chips. Each sinusoid is generated by a marginally stable second order IIR filter, and its frequency, amplitude and phase can be independently specified. The system is clocked at 60 MHz when working with a 44.1 kHz sampling rate. Two completely independent channels are available as output, and each sample relies on a 20 bit representation to achieve an SNR of at least 110 dB, thanks to the internal 24 bit word length. The IC is designed in a 0.5 /spl mu/m CMOS technology and has a core area of approximately 19 mm/sup 2/.

Two methods to design 1/fγnoise generators are reviewed and compared. The first one sums Lorentzian spectra obtained from the thermal noises of some resistors each one with a capacitor in parallel; the second one performs a proper filtering of a white-noise source. In that case, more precise considerations and more complete design rules are given.