Mixed-cell-height VLSI circuits are widely used to meet various design requirements. Due to design for manufacturability (DFM) considerations such as layout-dependent effects (LDEs), drain-to-drain abutment (DDA), and pattern coloring for multiple patterning, different spacings between adjacent cells affect performance, modeled as discrete spacing costs. A state-of-the-art dynamic programming (DP) approach can address this problem but can only handle a few cell rows simultaneously due to its high complexity. In this article, we propose a novel DP algorithm that can solve the problem optimally and more efficiently. Additionally, several optimality-preserving reduction techniques are employed to derive full-chip optimal solutions for large-scale designs. Experimental results demonstrate that the proposed approach significantly outperforms existing methods in terms of total spacing cost and total displacement.

Package design has become increasingly complex with the evolution of technology nodes and heterogeneous integration. To optimize timing performance and signal integrity, it is essential to separate different pairs of geometrically adjacent nets with distinct spacing values, which is referred to as the paired-spacing constraint. This paper presents the first free-assignment package routing algorithm flow considering the paired-spacing constraint. To minimize the routing resource demand and overall wirelength, we propose a dynamic programming-based net ordering method to maximize the number of nets with the same/similar spacing rules positioned next to each other. In addition, the free-assignment routing problem is elegantly solved with a minimum-cost maximum-flow problem on a delicately designed graph model. Experimental results show that the proposed flow can achieve 100% routability for the adopted industrial-modified benchmarks. In contrast, even with modifications to superficially consider paired spacings, a classic model experiences significant routability degradation.

As technology nodes advance and feature sizes shrink, wire resistance grows significantly, resulting in a substantial rise in circuit delays and reliability risks. Via pillars made up of multiple layers of parallel metals and vias can mitigate delay and electromigration by offering lower resistance and current density. However, it has become more and more challenging due to the increasing demand for inserting via pillars and the increasing density of power and ground (P/G) stripes in the lower layers. Moreover, an improperly designed via pillar structure can also block access to adjacent pins and worsen routability. In this paper, we propose comprehensive via pillar design strategies simultaneously considering flexible pin base selection, obstacle avoidance, and pin accessibility optimization. In addition, due to the high via pillar insertion rates advanced nodes target, we propose a congestion-aware via pillar design flow for high-density and closely positioned via pillars. Experimental results show that compared with a state-of-the-art work, our flow eliminates the design rule violations (DRVs) by 99% after via pillar insertion. In addition, by considering the pin accessibility of neighboring pins, our work also reduces over 98% DRVs after detailed routing.

Pin access has become one of the most significant challenges in large-scale full-chip routing due to the continuous reduction in feature sizes and the increasing complexity of designs. The conventional standard cell layout synthesis approaches usually optimize pin accessibility by maximizing pin lengths and access points. However, these predetermined pin patterns greatly occupy routing resources and may contrarily degrade routability. To address this problem, this paper proposes the first work of concurrent detailed routing with pin pattern re-generation to achieve ultimate pin access optimization. A pseudopin extraction and routing technique is proposed that can secure one access point for each input/output pin while allowing the remaining access points to be routable by other nets. The experimental results demonstrate that the proposed method can resolve 89% of local regions that are unroutable with original layout patterns without compromising power and timing performances.

With the announcement of the most advanced silicon spin quantum-bit (qubit) chip by Intel, silicon-based quantum circuit manufacturing technology has shown the superior potential to realize quantum computing to other technologies because of the mature semiconductor manufacturing technologies and the compatibility with electronics. Due to the bottleneck in scalability caused by interconnections in silicon-based quantum circuits, crossbar architectures serve as one of the most promising solutions for circuitry implementation. This paper proposes the first satisfiability modulo theories (SMT) formulation to optimally solve the layout synthesis problem by simultaneously performing scheduling, mapping, and routing for silicon-based quantum systems with a specific crossbar architecture. The experiments demonstrate that the proposed method can effectively generate layout synthesis results with minimal usage of swap and shuttle gates within the shortest circuit depths, and the solutions greatly outperform those derived from a state-of-the-art work.

Mixed-cell-height VLSI circuits have been popularly adopted to meet different design requirements. Due to various design for manufacturability (DFM)-related considerations, such as layout dependent effects (LDEs), drain-to-drain abutment (DDA), and pattern coloring for multiple patterning, different spacings in terms of placement sites between each pair of adjacent cells may result in different performances, which are usually modeled as discrete spacing costs. To tackle such a discrete and spacing cost-aware detailed placement problem for mixed-cell-height designs, a state-of-the-art dynamic programming (DP)-based approach can only tackle few cell rows simultaneously due to its extremely high complexity. In this paper, we propose a novel DP algorithm that can optimally and much efficiently solve the problem. In addition, several optimality-preserving reduction techniques are also proposed to enable the possibility of full-chip optimal solution derivation for large-scale designs. Experiments considering two DFM considerations show that the proposed approach greatly outperforms existing studies in terms of the total spacing cost, the total displacement, and runtime.