Asynchronous design style is quite appealing from various perspectives. In particular, several studies confirmed the reliability of asynchronous circuits in harsh environments, being capable to better tolerate power supply and temperature variations with respect to their synchronous counterparts. However, despite these advantages and many others, their applicability (especially in safety-critical scenarios) is quite limited today. Additionally, commercial EDA tools can be hardly used for asynchronous designs; hence, designers are discouraged of using such approaches for their applications. Notably, devices deployed for safety-critical applications must satisfy stringent requirements in order to guarantee the highest level of functional safety. Commonly, on-line testing mechanisms are necessary to achieve standards compliance. Such mechanisms undergo a validation process to assess their effectiveness, fault injection campaigns being the most commonly used. For doing so, designers exploit commercial EDA tools, intended to certificate standard compliance. In this paper, a methodology for the validation of Software Test Libraries (STLs) targeting on-line testing of asynchronous processor cores is proposed. The methodology is based exclusively on commercial tools, currently used in industry for functional safety analysis.

In recent years, use of FPGAs has been gaining more momentum for space applications as there are cases where using them can significantly reduce developments costs and time. In order to ensure correct operation in space, they have to be rad-hard, but most of such components are subject to ITAR. Atmel is the only provider for ITAR-free rad-hard FPGAs, but the default development flow provided leaves much to be desired. The contribution of this work is two-fold: First of all, we present a fully automated flow which improves the usability of the default development flow provided by Atmel, while requiring only a bare minimum of configuration for each design. Secondly, we show how to extend this flow in order to integrate external programs which can be used as in-place substitutions of steps of the default flow. Our experiments show that the proposed flow can significantly boost both the productivity of the designers and the QoR of the final implementations.

Two's complement multipliers are important for a wide range of applications. In this paper, we present a technique to reduce by one row the maximum height of the partial product array generated by a radix-4 Modified Booth Encoded multiplier, without any increase in the delay of the partial product generation stage. This reduction may allow for a faster compression of the partial product array and regular layouts. This technique is of particular interest in all multiplier designs, but especially in short bit-width two's complement multipliers for high-performance embedded cores. The proposed method is general and can be extended to higher radix encodings, as well as to any size square and m \times n rectangular multipliers. We evaluated the proposed approach by comparison with some other possible solutions; the results based on a rough theoretical analysis and on logic synthesis showed its efficiency in terms of both area and delay.

Variability is one of the fundamental problems faced by nano-scale electronic circuits and is expected to become even worse as process technology scales. Desynchronization is a design methodology, which converts a synchronous gate-level circuit into a more robust asynchronous one. In this paper, we describe the first fully-automated desynchronization design flow, based only on contemporary synchronous EDA tools and a new point tool for performing the desynchronization transformation. The flow was used to implement, down to mask layout level, a simple pipelined processor in a 90nm industrial library. We show that the desynchronization methodology can be easily integrated into contemporary industrial EDA flows. Results, on the design implemented, indicate that desynchronized circuits exhibit increased variability tolerance and better average case performance, for a small area and power overhead.