A 12-bit, 1-GS/s SAR-assisted pipeline ADC with background distortion and split-ADC-like gain calibrations is presented. The ADC includes an input buffer where its distortion is tackled by calibration. A low-cost auxiliary channel is introduced that serves as a reference for the calibration. It employs only a quarter of the input swing of the main channel, thus achieving adequate linearity. The auxiliary channel is further utilized for the gain calibration, where a split-ADC-like calibration is proposed to ease residue amplifier design constraint. The coefficients in the digital post-distortion filter are iterated through a multi-step multi-layer LMS algorithm, which converges faster and is more robust than its single-step counterpart. The buffered ADC works under a 1 V power supply thanks to the calibration, consuming 19.2 mW, where the input buffer contributes 18% of the total power. The calibration improves the SFDR by >14 dB within the 1st Nyquist zone, and >8dB up to 4th Nyquist input zone. The design achieves 59.3 dB SNDR and 67.1 dB SFDR at Nyquist input. The entire calibration converges within$1\times 10 ^{5}$iterations.

An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.

A new approach for automated synthesis of analog and mixed-signal systems is presented. The heterogeneous genetic optimization strategy starts from a functional description and evolves a simple design solution in a strict top-down design process to a complex one that fulfills multiple objectives. Transformations of both architecture and parameters are applied. The expected improvement of the violated objectives is used as driver for the transformation selection. The topology is really created, giving the opportunity to explore new architectures

This paper presents a framework for behavioral modeling of transceiver front-ends including sampled-data systems. The operation of the building blocks is described as an interaction in a multi-dimensional space between phases and/or frequencies. This description gives insight in the origin of non-ideal signals suggesting ways to improve the performance of the system. Its main application is the architectural exploration of RF architectures. Both continuous linear systems and sampling operations are mathematically represented by the basic operators of the phase-frequency transfer description: polyphase harmonic transfer matrices and distortion tensors. A Matlab-based implementation of the model demonstrates the usefulness of the model

In a generic behavioral model of an analog or mixed-signal electronic system, the internal and external signals and their interactions are formulated by more general descriptions than in commonly used behavioral models. This allows a more flexible design methodology. Whereas a behavioral model models an architecture of a system at a specific abstraction level, a generic behavioral model is built up out of generic functions that by specialization of these functions allows the modeling of a wide range of system architectures with different degrees of modeling accuracy. This enhanced abstraction level makes the approach suited for systematic analysis through refinement and architectural exploration of analog and mixed-signal building blocks and systems using computer-aided-design tools. As an application of this methodology, a generic behavioral model has been developed for continuous-time (CT) /spl Delta//spl Sigma/ analog-to-digital converters (ADCs) together with the specialization functions to take into account all major nonidealities at different levels of detail, including effects like jitter, saturation, and weakly nonlinear distortion. The results of experiments of a SystemC implementation of the model are presented. Compared to other models for analysis, the proposed method enables high accuracy even at low abstraction levels, whereas the event-driven character of the model results in short simulation times compared to time-marching simulations of behavioral models, written for example in very-high-speed-integrated-circuit (VHSIC) Hardware Description Language Analog and Mixed Signal (VHDL-AMS) or Matlab/Simulink. The flexibility of the model is demonstrated.

This paper presents a novel method for simulation of sampled systems with weakly nonlinear behavior. These systems can be characterized by adding weakly nonlinear terms to the linear state-space equations of the system resulting in an extended state-space model. Perturbation theory is used to split these equations in an ideal linear behavior and a non-ideal small perturbation. The linear equations are solved analytically which reduces simulation time compared to numerical evaluation. The solution of the perturbation equations is approximated by orthogonal polynomials. This methodology not only reduces simulation time compared to traditional numerical simulations, but also deals naturally with clock jitter and the discontinuous behavior of sampled systems. An implementation of the methodology has been used to analyze systems including switched filters and continuous-time /spl Delta//spl Sigma/ modulators.

A novel approach for the modeling of front-end architectures is presented. Architectures are described as a system transforming polyphase harmonic signals through building blocks modeled by polyphase harmonic transfer matrices and distortion tensors. The major goal of the method is to provide a model that is suited for systematic architectural exploration during front-end system design. An example of a downconversion architecture describes the system non-idealities as the result of parasitic transfers between phases and frequencies.

Circuit-level simulation of /spl Delta//spl Sigma/ modulators is a time-consuming task, taking one or more days for meaningful results. While there are a great variety of techniques and tools that speed up the simulations for discrete-time /spl Delta//spl Sigma/ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous-time counterpart. Nevertheless, in today's low-power, high-accuracy and/or very high-speed demands for A-to-D converters, designers are often forced to resort to the use of continuous-time /spl Delta//spl Sigma/ topologies. In this paper, we present a method for the high-level simulation of continuous-time /spl Delta//spl Sigma/ modulators as needed in top-down design and high-level modulator optimization. The method is based on analytical integration using behavioral models and exhibits the best tradeoff between accuracy, speed, and extensibility in comparison with other possible techniques that are reviewed briefly in this work. This methodology has been implemented in a user-friendly tool. Nonidealities such as finite gain, finite GBW, output impedance, and also nonlinearities, such as clipping, harmonic distortion, and the important effect of jitter are modeled. Finally, the tool was used to carry out some design-relevant experiments, illustrating the straightforward way of obtaining and exploring design tradeoffs at the modulator architectural level.

To reduce the long circuit-level simulation time of /spl Delta//spl Sigma/ modulators, a variety of techniques and tools exist that use high-level models for discrete-time (DT) /spl Delta//spl Sigma/ modulators. There is, however, no rigorous methodology implemented in a tool for the continuous-time (CT) counterpart. Therefore, we have developed a methodology for the high-level simulation of CT /spl Delta/E modulators and implemented this method in a user-friendly tool. Key features are the simulation speed, accuracy and extensibility. Nonidealities such as finite gain, finite GBW, output impedance and also the important effect of jitter are modelled. Finally, experiments were carried out using the tool, exploring important design trade-offs.

Circuit--level simulation of ΔΣ modulators is a time--consuming task (taking one or more days for meaningful results). While there are a great variety of techniques and tools that speed up the simulations for discrete--time (DT) ΔΣ modulators, there is no rigorous methodology implemented in a tool to efficiently simulate and design the continuous--time (CT) counterpart. Yet, in todays low--power, high--accuracy and/or very high--speed demands for A--to--D converters, designers are often forced to resort to the use of CT ΔΣ topologies. In this paper, we present a method for the high--level simulation of continuous--time ΔΣ modulators that is based on behavioral models and which exhibits the best trade--off between accuracy, speed and extensibility compared to other possible techniques that are reviewed briefly in this work. A user--friendly tool, implementing this methodology, is then presented. Nonidealities such as finite gain, finite GBW, output impedance and also nonlinearities such as clipping, harmonic distortion and the important effect of jitter are modeled. Finally, experiments were carried out using the tool, exploring important design trade--offs.