Gate-level fault simulation is a critical step in design for test and functional safety verification of the chip design process, essential to ensuring circuit reliability. As chip complexity grows for mission-critical applications such as autonomous vehicles, medical devices, and military systems, the efficiency of fault simulation increasingly becomes a bottleneck in the chip’s time-to-market. However, existing methods often suffer from computational redundancy, inefficiencies in memory access, or failure to optimize performance for specific CPU hardware platforms. This paper proposes DomSim, a hardware-aware hybrid fault simulation method that combines compiled simulation and event-driven simulation with an optimized computation-to-memory-access ratio. By utilizing circuit information and hierarchical structure provided by dominator trees, DomSim achieves high-quality circuit partitioning, optimizing hardware resource utilization and memory access locality. Furthermore, a parameter adjustment strategy tailored to hardware capabilities and circuit characteristics enables adaptive optimization. Extensive experiments show that DomSim surpasses a commercial tool by 10.29× on average. Further experiments demonstrate that DomSim exhibits good adaptability across different hardware platforms and circuits, highlighting the superiority of our method.

With the advancement of integrated circuit (IC) technology, the sensitivity to delay defects has significantly increased, rendering Transition Fault (TF) testing crucial for ensuring chip quality. However, as the complexity of IC designs increases, existing pattern parallelization methods are not flexible in detecting multi-cycle faults. In addition, the growing demand for simulation memory exacerbates inefficient memory access, becoming another critical bottleneck. This paper introduces ETPG (Efficient Transition fault simulation via dual-strategy Pattern parallelism and Gate restructuring), a novel TF simulation algorithm based on multi-dimensional optimization. The key innovations include an adaptive dual-strategy pattern parallel strategy that dynamically optimizes parallelization based on test pattern characteristics, enhancing efficiency and multi-cycle fault detection capability; a dual-dimension gate restructuring method that optimizes memory storage order, significantly reducing memory access time, particularly beneficial for large-scale circuits; and a collaborative mechanism between pattern processing and circuit storage optimization, achieving comprehensive performance improvements at both algorithmic and memory access levels. Experimental results demonstrate ETPG's significant performance improvements across various circuit scales, particularly for larger circuits. Compared to the synopsys commercial tool testmax (TMAX), ETPG achieves average speedups of 2.846× for circuits below 100k gates and 4.428× for circuits above 100k gates.

Deep learning has significantly advanced Electronic Design Automation (EDA), with circuit representation learning emerging as a key area for modeling the relationship between a circuit’s structure and functionality. Existing methods primarily use either Large Language Models (LLMs) for Register Transfer Level (RTL) code analysis or Graph Neural Networks (GNNs) for netlist modeling. While LLMs excel at high-level functional understanding, they struggle with detailed netlist behavior. GNNs, however, face challenges when scaling to larger sequential circuits due to long-range information dependencies and insufficient functional supervision, leading to decreased accuracy and limited generalization. To address these challenges, we propose MOSS, a multimodal framework that integrates GNNs with LLMs for sequential circuit modeling. By enhancing D-type Flip-Flop (DFF) node features with embeddings from fine-tuned LLMs on RTL code, we focus the GNN on critical anchor points, reducing reliance on long-range dependencies. The LLM also provides global circuit embeddings, offering efficient supervision for functionality-related tasks. Additionally, MOSS introduces an adaptive aggregation method and a two-phase propagation mechanism in the GNN to better model signal propagation and sequential feedback within the circuit. Experimental results demonstrate that MOSS significantly improves the accuracy of functionality and performance predictions for sequential circuits compared to existing methods, particularly in larger circuits where previous models struggle. Specifically, MOSS achieves a $\mathbf{9 5. 2 \%}$ accuracy in arrival time prediction.

As functional safety of electronic chips gains importance in autonomous vehicles and aerospace, standards like ISO 26262 mandate high diagnostic coverage, requiring extensive gate-level fault simulations. However, for large-scale industrial sequential circuits, these simulations are time-consuming, creating a significant bottleneck in chip development. Prior approaches have focused on reducing computational complexity and optimizing CPU hardware usage by minimizing redundant computations during fault propagation and leveraging bit-level parallel processing capabilities. Techniques like parallel-pattern and event-driven simulations have improved performance in combinational circuits but face limitations in sequential circuits due to timing dependencies within loops. The challenge lies in parallelizing simulations across different cycles without violating these dependencies, which is exacerbated by the complex feedback structures in SCCs. In this work, we propose a novel parallel-pattern fault simulation framework that combines loop fusion with efficient event traversal to accelerate sequential circuit simulations. By compiling simple loops into larger nodes, we reduce the number of feedback events without introducing excessive redundancy. For larger SCCs, we develop specialized algorithms for selecting loop entrance nodes based on indegree analysis and implement the lazy propagation strategy for internal nodes. This approach minimizes simulation events caused by inaccurate predictions and reduces overhead associated with false event propagation. We integrate these techniques into our simulation framework, EPICS, which strategically mixes compiled and event-driven simulations to optimize performance. Experimental results demonstrate that EPICS achieves a $5.94 \times$ speedup over state-of-the-art commercial tool while maintaining the same fault coverage.

Fault simulation is a fundamental component in the design for testability (DFT) processes, especially in automatic test pattern generation (ATPG). Various approaches have been proposed to enhance the efficiency of fault simulation on multi-core systems. However, these approaches have not taken full consideration of the intrinsic characteristics of deterministic patterns. Deterministic patterns are generated by ATPG and are predominantly employed in practical applications rather than random patterns. In this paper, we introduce DDP-Fsim, a fast and scalable fault simulator on multi-core systems. DDP-Fsim capitalizes on the distinctive nature of deterministic patterns, wherein a small subset of patterns can effectively detect the majority of faults. Initially, DDP-Fsim parallels in fault dimension by dynamically scheduling fanout-free regions (FFR) to handle easy-to-detect faults. Subsequently, it parallels in pattern dimension by dynamically scheduling patterns to address the remaining hard-to-detect faults. Experiments demonstrate that on a 24-core system, DDP-Fsim is 10× faster than the commercial tools for full-scan circuits and deterministic patterns. Additionally, DDP-Fsim with 24 cores achieves an average speed-up of 16× compared to its single-core execution, while the commercial tools with 24 cores achieves only 3×-6× speed-up than their single-core execution. This indicates the significantly superior scalability for DDP-Fsim.

In applications such as automotive chips that require high service responsiveness, ensuring the functional safety of electronic systems is crucial. The prevalent method involves conducting Failure Modes, Effects, and Diagnostic Analysis (FMEDA) and fault simulation at the design verification stage to assess safety levels. However, existing approaches primarily analyze at the register transfer level (RTL), which does not reflect the actual structure of chips where faults occur at the gate level, resulting in inaccuracies. This is due to the slower analysis speed at the gate level, making it challenging to balance precision with speed, thus defaulting to RTL for simulation. To address these challenges, we propose an innovative method for functional safety analysis and verification that integrates advanced gate-level fault simulation technology with FMEDA techniques. Our approach is based on an enhanced gate-level FMEDA framework, enabling deeper and more accurate safety performance analysis. Through experimental verification, our method has proven to be over 3 times faster than commercial tools in fault simulation, significantly enhancing the reliability and speed of the functional safety process. Ultimately, our research provides rapid and precise safety analysis and verification at the gate level for high-risk applications like automotive chips, offering robust technical support and practical guidelines for advancing functional safety technology in this sector.