The energy consumption in heterogeneous computing systems (HCS) has attracted a great deal of attention in both scientific and commercial fields due to operating and environmental concerns. Based on the technique of dynamic voltage and frequency scaling (DVFS), many studies have investigated and developed efficient task scheduling algorithms for energy reduction. However, most of them provide only one refined frequency for each task to perform slack reclamation. Moreover, the total energy-saving is accumulated by individual local minimum of energy consumption with less or no global consideration. In this paper, we use a linear combination of processor frequencies to execute each task and allocate time slices for these frequencies by a linear programming approach. The goal of energy reduction is represented by a global function associated with the set of time slices while the constraint declarations are given by runtime precedence-constraints and processor-constraints, respectively. In this case, the problem of energy-efficient task scheduling becomes a linear program which can be solved by a mature set of linear programming solvers. The experimental results show the effectiveness of our proposed method and demonstrate the superior performance over existing approaches without sacrificing the schedule length.

As different chips are stacked together in 3D ICs, the power/ground (P/G) network simulation becomes more challenging than that of 2D cases. In this paper, we propose a hierarchical simulation method suitable for 3D P/G network (HS3DPG), which can ensure full parallelism and good scalability with the number of tiers. In the IR drop analysis, when there are 9 tiers, the hierarchical method can be 6.5 times faster than the direct full network simulation. The accuracy of HS3DPG has been verified by a 3D P/G network from the industrial design. Besides, we introduce the “locality” property into HS3DPG to further simplify the simulation. Finally, HS3DPG is used to analyze the voltage distribution of a 3D P/G network with clustered TSVs.

For the node chips of wireless sensor networks (WSN), low power and fast settling are the two most important factors. In this paper, a low-power fast-settling phase-locked loop (PLL) frequency synthesizer working at 1.72 GHz∼1.74 GHz is designed for a 100 kb/s gauss frequency shift keying (GFSK) WSN transceiver. Low power consumption is realized by a bond-wire voltage-controlled oscillator (VCO) and a multi-stage power-scaling prescaler. Instead of conventional diode-based electro-static discharge (ESD) protection, resistor-based ESD protection is proposed for the bond-wire VCO to decrease the parasitic capacitance so that the automatic frequency calibration (AFC) range is enlarged by 50%. In addition, a dynamic-bandwidth scheme is proposed to meet the requirements of time-division half-duplex WSN systems. The chip is implemented with HJTC 0.18 µm CMOS technology. Measured results show that the PLL consumes 10.6 mW and settles within 18 µs including the AFC process; the phase noise is −91.9 dBc/Hz@10 kHz and −119.3 dBc/Hz@1 MHz under the receiving (Rx) state, and −95.2 dBc/Hz@10 kHz and −116.8 dBc/Hz@1 MHz under the transmitting (Tx) state.

In this paper, a simple, efficient, low power off-chip memory design is proposed, which fully exploits the features of DRAM memory and video application, as well as overcomes the drawbacks of algorithm complexity and system modification of embedded compression, which is a popular way to decrease power consumption of the off-chip memory. The integration of the scheme into video decoder will not involve any extra video decoding complexity. It adopts the simple bus-invert encoding scheme. Based on the fact that the power consumption of logic `0' bit is less than that of logic `1', bus-invert encoding scheme is applied to the transferring data between video decoder and off-chip memory. Meanwhile, the features of fault tolerance of human eyes and lossy processing of video decoding application are exploited to solve the extra flag-bit of encoder scheme in off-chip SDARM memory, which has the fixed bit width and is less flexible than on-chip SRAM. This scheme is integrated into MPEG-2 decoder system. The experiment results show that this scheme can archive 20%-35% reduction in power consumption of logic `1' bit, and the objective quality of image has about 1.5db PSNR improvement on average.

In this paper, we propose an energy efficient architecture of wireless sensor network node. It consists of a general-purpose processor and several compression accelerators. To verify the low energy consumption of this architecture, we implement a baseband chip of sensor node by 1-poly 6-metal 0.18um CMOS technology, in which a hardware accelerator is realized based on a distributed wavelet compression algorithm. Our measurements show that the compression accelerator based architecture reduces over 98% energy consumption compared with the traditional solution.

Sleep transistor (ST) insertion is a valuable leakage reduction technique in circuit standby mode. Fine-grain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improve circuit noise margins. In this paper, we introduce a novel two-phase FGSTI technique which consists of ST placement and ST sizing. These two phases are formally modeled using mixed integer linear programming (MILP) models. When the circuit timing relaxation is not large enough to assign ST everywhere, leakage feedback (LF) gates, which are used to avoid floating states, induce large area and dynamic power overhead. An extended multi-object ST placement model is further proposed to reduce the leakage current and the LF gate number simultaneously. Finally, heuristic algorithms are developed to speed up the ST placement phase. Our experimental results on the ISCAS'85 benchmarks reveal that: 1) the two-phase FGSTI technique achieves better results than the simultaneous ST placement and sizing method; 2) when the circuit timing relaxation varies from 0% to 5%, the multi-object ST placement model can achieve on average 4times-9times LF gate number reduction, while the leakage difference is only about 8% of original circuit leakage; 3) our heuristic algorithm is 1000times faster than the MILP method within an acceptable loss of accuracy.

A clock and data recovery (CDR) circuit is proposed based on the sigma-delta quantization. The phase of the new CDR circuit is adjusted by a sigma-delta modulated reference clock that increases the stability of the system and can easily interface with PLL cores embedded in FPGAs. The approximate linear model of the proposed CDR is analyzed for SONET/SDH applications to evaluate its performance. The measurement shows that the jitter tolerance meets the ITU-T requirement with a high margin of 0.3UI. The commercial equipment has been developed using a single FPGA chip based on the SDM-CDR

Multi-threshold CMOS is a valuable leakage reduction method in circuit standby mode. Reducing leakage current through fine-grain sleep transistor insertion (FGSTI) makes it easier to guarantee circuit functionality and improves circuit noise margins. In this paper, we first indicate the negligible dependence of ST size on the amount of leakage saving which makes the two-phase FGSTI reasonable based on our leakage current and delay models. Then we introduce a novel two-phase FGSTI technique: a) ST placement and b) ST sizing, which are formally modeled as two linear programming (LP) models respectively. Our experimental results show that the two-phase FGSTI technique can achieve 78.91%, 92.55%, 97.97% leakage saving when the circuit slowdown is 0%, 3%, 5% respectively. Comparing to the simultaneous ST placement and sizing method using mix integer linear programming (MLP) [1], our technique leads to on average 2% more leakage current reduction while at least 10X runtime saving since fewer variables and constraints with less approximation are used in the LP models. When the circuit slowdown is large enough to perform conventional fixed slowdown method, our technique can still achieve 75.48% ST area saving. Moreover, we show that when the circuit slowdown is 0%, it should be carefully considered to use FGSTI technique due to a large amount of leakage feedback gates.

In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with capacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.

Nonlinear functions can be approximated by the linear combination of base functions, which provides a road towards the analog synthesis. An improved Simulated Annealing Algorithm (SA) for nonlinear function approximation and a universal implementation of analog circuits are presented in this paper. Synthesis results demonstrate the validity and efficiency of the proposed approach.