EDBT 2026 Demo / reviewers in the wild / expert
Bhawna Aggarwal
dblp:39/7690
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7ranked-venue papers
1as first author
7since 2021 · last 2026
0000-0002-4165-0320ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7 · 1 first-author · 7 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | New memtranstor emulator using DVCCTA and OTA with its application
Rupam Das, Shireesh Kumar Rai, Bhawna Aggarwal |
Integr. | 3 |
| 2025 | Design of a new compact multiplier-less memtranstor emulator and its application in neuromorphic and chaos generationabstractThis paper presents a compact configuration of memtranstor (MT), a new memory element having direct relation between magnetic flux (φ) and charge (q). The proposed configuration offers a simple architecture as it is designed without the need of any multiplier or any other complex component. This emulator has been realized by employing one operational transconductance amplifier (OTA), one current differencing transconductance amplifier (CDTA), and one voltage differencing current conveyor (VDCC) along with a few passive components. The emulator captures the fundamental relationship between φ and q, enabling the realization of distinctive pinched hysteresis loops under sinusoidal excitation, a hallmark of memtranstive behavior. It is designed to operate at a supply voltage of ±1.25 V. The circuit offers tunability through the variation in biasing voltages ensuring flexibility for a wide range of applications. The accuracy and dynamic characteristics of the proposed architecture are verified through mathematical analysis and LTSpice simulations with a 180 nm CMOS model. To assess the behavior of the proposed emulator in real environment, process-voltage-temperature analysis has been carried out followed by the designing of full custom layout in an area of 4464.88 μm 2 . Furthermore, non-ideal analysis has been carried out considering the parasitic elements at various terminals of the blocks employed in the circuit design. Additionally, to prove the practical feasibility of the proposed circuit, its operation has been confirmed by macro-models of the designated ICs followed by the bread-board implementation using commercial ICs under ±12 V supply voltage. To demonstrate practical utility, the emulator is employed in two key applications: an artificial synapse for neuromorphic systems and a nonlinear chaotic oscillator, both showcasing its relevance for next-generation memory-driven analog computing. The proposed design stands out due to its low component count, compact design, and ease of integration, making it a promising candidate for emerging fields like neuromorphic engineering and chaos-based systems. Furthermore, it provides valuable insights for future research in MT-based nonlinear dynamics and holds significant potential for advancing MT driven applications in neuromorphic computing and beyond. Manoj Kumar 0032, Shireesh Kumar Rai, Bhawna Aggarwal, Maneesha Gupta |
Integr. | 3 |
| 2025 | Design and analysis of VDIBA-based chaotic oscillators and their applications in communication system
Kushal Kumar, Akshay Rana, Shireesh Kumar Rai, Bhawna Aggarwal |
Integr. | 4 |
| 2024 | A low-voltage MOS translinear loop, biased using FVF and its applications in realizing square-rooter and squarer circuits
Aakriti Chhabra, Bhawna Aggarwal, Raj Senani |
Integr. | 2 |
| 2024 | Nature inspired algorithm based design of near ideal fractional order low pass Chebyshev filters and their realization using OTAs and CCII
Ritu Daryani, Bhawna Aggarwal |
Integr. | 2 |
| 2024 | Meminductor emulators using off-the-shelf active blocks with application in chaotic oscillator
Shireesh Kumar Rai, Bhawna Aggarwal, Vikas Singroha |
Integr. | 2 |
| 2023 | New memristor-less, resistor-less, two-OTA based grounded and floating meminductor emulators and their applications in chaotic oscillators
Bhawna Aggarwal, Shireesh Kumar Rai, Anant Sinha |
Integr. | 1 |