Satellite Internet (SI) is an essential component of 6G as an effective supplement to terrestrial Internet in the future. Owing to its relatively limited processing power and bandwidth, distributed denial of service (DDoS) attacks may cause substan-tial damage. Moreover, the complexity and difficulty of defense also increase due to the constantly changing topology scale of SI when supporting various applications. Therefore, path tracking must be maintained with high precision at different scales to realize protection at the boundary. However, the marking rate limits traditional packet marking methods, causing a decrease in the tracking accuracy when the topology is expanded. Therefore, we propose a scalable traffic path tracking (TPT) scheme. Firstly, a lightweight description of malicious traffic in the entire network is realized by improving a multi-dimensional traffic feature digesting method. Secondly, the connection relationship sparse matrix of nodes is obtained based on the Hidden Markov Model modeling of the network topology and attack scenarios. These generate the observation probability matrix B and transition probability matrix A of the traditional Viterbi algorithm. Finally, we optimize the Viterbi algorithm by adding an index matrix of the next-largest probability value to eliminate tracking loops, thereby achieving high tracking accuracy for topologies of different scales. The Keysight Ixia platform is used to generate malicious traffic in the experiments. The results demonstrate that the scheme can maintain a tracking accuracy of over 99 % against various DDoS attacks in topologies of different scales, which is more accurate and scalable than existing methods.

Satellite Internet (SI) dramatically expanded the ground-based Internet, and it is also the future direction of 6G. However, due to limited computing power and bandwidth resources, Distributed Denial-of-Service (DDoS) attacks can cause more severe damage to SI, and even paralysis of the entire network. Current DDoS defense mechanisms are built on abundant computing power and bandwidth resources, making applying in the SI scenario challenging. Aiming at protecting SI from DDoS attacks, a blockchain-based distributed collaborative entrance defense (DCED) framework is proposed, in which network traffic characteristics can be recorded and aggregated at the entrances of SI. The proposed framework consists of a distributed detection digesting procedure, a digest virtual aggregation procedure, and an entrance control strategy. The former procedure detects and extracts multidimensional characteristics of DDoS attacks and pushes them onto the blockchain. The latter procedure collects block data and aggregates attack features using the MapReduce algorithm and then compares them with baseline and gives an alert. The strategy completes the filtering and interception of traffic. Experiments use the IXIA platform to generate malicious traffic, and results show that the framework can accurately identify attack traffic within 1500 ms, reaching an area of 0.99 under the receiver operating characteristic curve. The proposed framework is more effective than other similar DDoS methods, protecting the precious SI bandwidth resources.

The secure wireless fieldbus system faces error diffusion problem. When Advanced Encryption Standard (AES) adopted, even few errors in the channel spread, causing half of the data corrupted in an AES block. It significantly degrades the system reliability. In this work, we first design a new secure communication architecture to tackle the error diffusion effect, without compromising the system latency. Our novel hierarchical architecture is implemented in two dimensions. At the transmitting end, the first dimension performs encryption followed by short code encoding. Accompanying, a long code encoding is performed in parallel in the second dimension. While at the receiving end, the first dimension of the short code decoding and decryption, and the second dimension of the long code decoding are performed serially. Then, we conduct theoretical and practical analyses of error performance. Both theoretical and practical simulations show that our hierarchical architecture achieves a steeper bit error rate (BER) curve than the traditional architecture. At the BER of 10-6, the hierarchical architecture using (252,128) BCH in first dimension and (8128,7296) BCH / (8060,7040) LDPC in the second dimension achieves 0.25 / 1.3 dB performance gain than the traditional architecture only using (252,128) BCH code.

The satellite communication systems continually increase the bandwidth to support high-throughput applications. However, the sampling rate of the analog-digital converter (ADC) limits the performance of the system. A dedicated receiver structure is proposed for IQ-separated sampling to support ultra-high sampling rate. This paper designs the key modules of the structure, including frequency error estimation, frame location and timing synchronization. The algorithm for the modules is descripted and the details of realization are focused. The simulation results demonstrate reasonable performance of the designed modules.

Wireless on-board bus system can not achieve the same performance of transmission delay and th roug hput when compared to the wired one. In this paper a multi-channel media access control (MAC) protocol is proposed. The protocol takes advantage of the coexistence of the multiple chan nels pro vided by the wireless standard. Three consecutive session, request session, schedule session and transmission session, make up the superframe in the star topology. In order to handle pac kets of different real-time requirements efficiently, packets produced in each slave node are divided into three queues of different quality of service $(~\mathrm {Q}\mathrm {o}\mathrm {S})$. During the schedule session, the earliest deadline first (EDF) scheduling based on the global queue achieves the better channel utilization when it is only ex ecuted on the lo cal one. Simulation results indicate that the proposed multi-channel MAC protocol achieves better performance of transmission delay and throughput.

Spin-transfer torque random access memory (STT-RAM) is a promising emerging memory technology in the future memory hierarchy. However, its unique reliability challenges, i.e., the asymmetric bit failure mechanism at different bit flippings, have raised significant concerns in its real applications. Recent studies even show that the common memory error repair “remedies” cannot efficiently address them. In this article, we for the first time systematically study the potentials of the strong low-density parity-check (LDPC) code for combating such unique asymmetric errors in both single-level-cell (SLC) and multi-level-cell (MLC) STT-RAM designs. A generic STT-RAM channel model suitable for the SLC/MLC designs, is developed to analytically calibrate all the accumulated asymmetric factors of the write/read operations. The key initial information for LDPC decoding, namely asymmetric log-likelihood ratio (A-LLR), is redesigned and extracted from the proposed channel model, to unleash the LDPC’s asymmetric error correcting capability. LDPC codec is also carefully designed to lower the hardware cost by leveraging the systematic-structured parity check matrix. Then two customized short-length LDPC codes—(585,512) and (683,512)—augmented from the semi-random parity check matrix and the A-LLR based asymmetric decoding, are proposed for SLC and MLC STT-RAM designs, respectively. Experiments show that our proposed LDPC designs can improve the STT-RAM reliability by at least 10 2 (10 4 ) when compared to the existing error correction codes (ECCs) for the SLC (MLC) design, demonstrating the feasibility of LDPC solutions on STT-RAM.

Spin-transfer torque random access memory (STT-RAM) is a promising technology for future nonvolatile caches and memories. To increase the storage density, multilevel cell (MLC) technique was recently introduced to STT-RAM designs at the cost of degraded access speed, reliability, and energy efficiency. Existing MLC STT-RAM cache architectures primarily focus on the performance and energy optimizations but ignore the crucial demand for reliability. In this paper, we propose “TriZone”-a holistic design scheme for MLC STT-RAM cache to simultaneously meet the requirements of performance, energy, and reliability. Three cache block configurations, namely hard, soft, and mixed, are constructed with the hard-bit, soft-bit, and both hard-bit and soft-bit of MLC STT-RAM, respectively. By observing the difference of these cache blocks, a nonuniform strength ECC (NUS-ECC) is developed to guarantee the operational reliability of a cache block with a variable decoding delay adapting to the needs of error correction (e.g., the number of the erroneous bits). The whole MLC STT-RAM cache is then partitioned into three regions, each of which is composed of different cache blocks. In order to achieve the best tradeoff among performance, energy, and reliability, we then introduce the dynamic cache partitioning to determine the partition of this tri-way MLC STT-RAM cache according to the runtime characteristic of various applications. Experiment results show that compared with conventional performance-driven MLC STT-RAM cache design with pessimistic ECC, TriZone can improve the system performance and energy by averagely 11.7% (10.0%) and 13.3% (15.7%), respectively, for single-threaded (multiprogram) applications. The additional area overhead associated with NUS-ECC is limited by ~ 3%.

As technology moves into nano-realm, large area of the chip is especially vulnerable to single event upset (SEU) in space applications. In this paper, low cost fault-tolerant schemes are presented for the key modules of Low-Density Parity-Check (LDPC) code decoder to save logic resources. For counters, a fault-tolerant scheme based on m-sequence and Hamming coding is proposed, whereby the soft errors generated by SEUs can be located and corrected by a simple Hamming decoder. For RAM contents, we first propose a layered pipelined architecture absorbing LLR RAM into V2C RAM to reduce memory bits, which will lower the impact of SEUs. Then, a RAM hardening scheme is proposed, which only requires to detect soft errors by parity check, while the error correction is accomplished by decoder's own iterative decoding capability that has not been exploited sufficiently. Simulation results show that the proposed fault-tolerant counter could totally avoid SEUs and saves 42% of cell area compared with TMR method and the layered pipelined architecture saves 42% and 12% of memory bits compared with [4] and [15]. In addition, the hardened RAM cells will not cause extra bit errors when a soft error happens under the environments of high signal-to-noise ratio (SNR). The cost is only one parity bit for each RAM content, which is much less than conventional hardening schemes.

The quasi-cyclic low-density parity-check (QC-LDPC) codes have attracted much attention in space communication systems. However, the decoders are still difficult to be applied in practice for their large area and high memory requirements. Moreover, the clock cycles for the input and output interfaces can not be ignored due to the I/O resource is also limited on this occasion, which influences the throughput improvement significantly. This paper presents a parallel pipelined decoder architecture for QC-LDPC codes, which can largely reduce their area and memory size while maintaining a fast convergence speed. The decoding approach reformulates the original normalized min-sum algorithm and adopts a two pipelines architecture to eliminate the clock cycles for the I/O and reduce the number of clock cycles per iteration. Chip designed with TSMC 0.13-µm eight-metal-layer standard CMOS technology shows that it can achieve a throughput up to 767 Mbps with only 3.12 mm2core area consumption. Especially, only 36 I/O ports are occupied, less than 10% of the conventional decoders.

In indoor UWB TDoA localization systems, anchor clock drifts, RF and ADCs front end delay and their long term variation are main performance limiting factors. Anchor synchronization using reference tags instead of wired lines are promising for ease of deployment In this work, an error analysis on UWB TDoA localization system with reference tag is performed, focusing on propagation and clock drifts. A 500 MHz experimental UWB localization system with reference tag was built. Using single carrier UWB signal with a 127 chip PN code, the smallest TDoA measurement error is 21.7 cm and the worst error is 45.3 cm, as was shown by the test results.

Noise uncertainty, which is unavoidable in practice, can severely limit the detection performance of cooperative spectrum sensing. Derived from the conventional hard combination scheme, the improved one-out-of-N rule is presently the most effective algorithm to reduce the influence of noise uncertainty. However, in this algorithm the abandonment of local test statistic when it falls in the uncertainty region may lose some useful information. In this paper, first we analyze the optimality of the improved one-out-of-N rule and indicate that there should be an optimal number of cooperative users that minimizes the total error rate. Then, a new weighted hard combination scheme which makes full use of the uncertainty region is further proposed. The optimizations of weight coefficient and user number in this new scheme are also investigated. Numerical results show that the minimal total error rate and its corresponding user number of this scheme are both lower than those of the improved one-out-of-N rule.

While channel state information (CSI) at the transmitter is critical to the system capacity of multiple input multiple output (MIMO) broadcast channels, its acquisition is practically intricate. This paper offers an alternative and investigates a special MIMO broadcast channel, which exploits the benefit of receiver cooperation and renders it unnecessary to acquire CSI at the transmitter. The cooperation gain is studied in a system-wide perspective by taking into account the resource (power and bandwidth) consumed to establish the cooperation links. Built on that, the generalized cooperation spectral efficiency is defined.With a dedicated approximation, a near optimal resource allocation strategy is presented to maximize the cooperation spectral efficiency. Specially, the power allocation problem is simplified into a polynomial rooting problem. Simulation results show that the receiver cooperation can provide a performance gain and achieve the MIMO capacity. Moreover, performance loss incurred by the proposed method is negligible compared to the numerical exhaustive search scheme.

The frequency selective fading channels cause severe inter-symbol interference (ISI) and significantly degrade the bit error rate (BER) performance of broadband wireless communication systems. In this paper, a soft detection algorithm employing the idea of QR decomposition, data grouping and successive interference cancelation (SIC) is proposed for coded single carrier (SC) block transmission. We show that SC block transmission with unique word (UW) brings two unique features while employing the QRD detection method. We refer to them as the natural ordering property and the sparse property, respectively. The data block is divided into small groups and the log-likelihood ratio (LLR) of each element is derived from the bottom up. A flexible tradeoff between BER performance and detection complexity can be provided. Simulation results show that in frequency selective fading channels, the proposed scheme can obtain dramatic performance gain compared to the minimum mean square error (MMSE) single carrier frequency domain equalization(FDE) with low complexity.

In this paper, a novel spread dimension (SD) communication using orthogonal patterns to transmit information is proposed to achieve the reliable communication with the smarty jamming. A soft demodulator is presented and a posterior probability (APP) according to maximum a posterior probability (MAP) estimation is derived to obtain the soft information for soft iterative decoding. The demodulator is suitable for coherent reception ,non-coherent reception with the channel state information (CSI) and non-coherent reception without CSI. Besides, the capacity of the coded modulation scheme which employs GF(q) LDPC codes is compared with the bit interleaved coded modulation (BICM) scheme using the binary LDPC codes for the SD communication system. We prove that the CM scheme is able to better utilize the soft information and owns a higher achievable rate. Simulation results show that the gain of the q-ary LDPC coded SD system is up to 0.5 dB over AWGN channel and has a very good performance with the smarty jamming.

In deep space communications, the received signals are always highly dynamic and very weak, which makes it quite challenging to achieve reliable data reception. To tackle these problems, a robust algorithm which joins tracking and code‐aided synchronisation is proposed in this study. The frequency lock loop‐assisted phase lock loop is used as the tracking loop, which integrates the characteristics of both outstanding dynamic performance and precise measurement. The code‐aided synchronisation is adopted as the demodulation and decoding loop, which utilises the relationship among the coded symbols to assist signal demodulation under the low signal‐to‐noise ratio condition. It is worth pointing out that the power tradeoff between the main carrier and subcarrier signals which operate in the two loops mentioned above is also optimised to minimise the total transmitting power. Simulation results showed that the proposed scheme with code rate 1/5 low‐density parity‐check codes could almost eliminate the effect of these factors, with the excellent performance, which closely approximates the ideal decoder in additive white Gaussian noise channel.

The time-frequency interleave (TFI) diversity scheme for single carrier block transmission with frequency domain equalization (SC-FDE) has been proposed. For single antenna wireless communication systems, it can provide frequency diversity in frequency selective channels by interleaving and retransmitting. In this article, the iterative block decision feedback equalization (IBDFE) structure for TFI diversity scheme is proposed. Both the feed-forward filter (FFF) and feed-backward filter (FBF) work in the frequency domain, which makes the implementation complexity low. The FFF and FBF coefficients based on minimum mean square error (MMSE) criterion are derived. The correlation between the transmitted symbols and the detected symbols are estimated in a simple iterative manner. Simulation results show that for TFI diversity scheme with IBDFE, a much better bit error rate (BER) performance can be obtained than TFI with frequency domain linear equalizer (FD-LE) only for one more iteration. Compared to IBDFE without TFI diversity, the performance gain is impressive.