Compute Express Link (CXL) is an advanced inter-connect standard designed to facilitate high-speed communication between CPUs, accelerators, and memory devices, making it well-suited for data-intensive applications such as machine learning and real-time analytics. Despite its advantages, CXL memory encounters significant latency challenges due to the complex hierarchy of protocol layers, which can adversely impact performance in latency-sensitive scenarios. To address this issue, we introduce the Speculative Protocol Bypassing (SPB) architecture, which aims to minimize latency during read operations by speculatively bypassing several protocol layers of CXL. To achieve this, SPB employs the Snooper mechanism, which extracts essential read commands from the packet data at an early stage, allowing it to bypass multiple protocol layers and reduce memory access time. Additionally, the Hazard Filter (HF) prevents Read-After-Write (RAW) hazards between read and write operations, thereby maintaining data integrity and ensuring system reliability. The SPB architecture effectively optimizes CXL memory access latency, providing a robust solution for high-performance computing environments that require low latency as well as high efficiency. Its minimal hardware overhead makes it a practical and scalable enhancement for future CXL-based memory.

Solid-state drives (SSDs) are widely used in cloud storage. As the capacity of an SSD has been increasing, it has become common for many virtual machines (VMs) to share a single SSD to maximize resource utilization. However, this sharing can degrade the efficiency of internal operations, such as garbage collection, resulting in increased latencies. Existing literature in this field has mostly focused on interdevice isolation considering the storage device as a black-box entity or presumed an SSD to be shared by up to only eight VMs. In this study, we first analyze a realistic SSD usage environment in cloud systems and identify that block-level data isolation (BDI) should be guaranteed to efficiently scale up the number of VMs in an SSD with minimum latency increases. However, previous schemes cannot work efficiently with BDI when the SSD is shared by dozens of VMs. Based on this analysis, we propose an SSD internal resource management scheme in a cloud environment, called highly VM-scalable SSD (VMS). VMS dynamically partitions physical resources and allocates them to VMs, while the VMs share global buffer blocks to lower latency during abrupt fluctuations of write I/O intensities. Our experimental results show up to 29% of latency reduction. VMS exhibits reduced latencies even in the experiment with 64 VMs, where existing schemes do not function normally.

Recent NAND flash memories provide a partial read operation that can read a page partially and has lower latency than a normal read operation. In order to maximize the benefit of the partial read operation, compression techniques can be applied to improve performance by generating additional partial page requests by compressing pages into smaller ones. Unfortunately, existing compression support SSDs suffer from a huge decompression latency that eventually cancels the benefit of the partial read operation. In this paper, we propose Partial Read-aware SSD (PR-SSD) for fully exploiting partial read operations. In order to mitigate the decompression latency, we propose a new compression algorithm, called Dominant Pattern Compression (DPC), which has extremely low decompression latency. Because uncompressed page requests cannot exploit the partial read operation, we propose split Flash Translation Layer (FTL) that can split the requests into smaller ones and allocate them to different channels for exploiting channel-level parallelism in SSD. Experimental results reveal that PR-SSD can reduce the read response time by 18% on average and also the number of writes and write response time by 29% and 24% on average, respectively

Recent research has revealed that runtime bad blocks are found in the early lifespan of solid state drives. The reduction in overprovisioning space due to runtime bad blocks may well have a negative impact on performance as it weakens the chances of selecting a better victim block during garbage collection. Moreover, previous studies focused on reusing worn-out bad blocks exceeding a program/erase cycle threshold, leaving the problem of runtime bad blocks unaddressed. Based on this observation, we present a salvation scheme for runtime bad blocks. This paper reveals that these blocks can be identified when a page write fails at runtime. Furthermore, we introduce a method to salvage functioning pages from runtime bad blocks. Consequently, the loss in the overprovisioning space can be minimized even after the occurrence of runtime bad blocks. Experimental results show a 26.3% reduction in latency and a 25.6% increase in throughput compared to the baseline at a conservative bad block ratio of 0.45%. Additionally, our results confirm that almost no overhead was observed.

The increased flash page sizes cause a large number of subpage requests due to the difference in host and flash I/O units. The subpage requests may degrade the space utilization, response time, and lifetime of NAND flash memories. Addressing the subpage issue, a few studies in the past have proposed merging subpages to generate full pages. Although these subpage schemes may improve performance and lifetime, they incur immense DRAM space for storing the sector information of merged pages. Moreover, they do not consider the update frequencies of the subpages for merging and thus an update request to a subpage causes partial page invalidation, which leads to garbage collection (GC) overhead. To address these issues, our proposed scheme considers the update frequencies of the subpages for merging in order to avoid partial page invalidation, which in turn improves the GC efficiency. Further, the proposed scheme uses a sector information table (SIT) in flash pages to store the fine-grained sector information of merged subpages. In the light of experiment results, our scheme, on average, reduces DRAM footprint, flash writes, and block erasures by 29%, 18%, and 13%, respectively.

A solid state drive (SSD) receives requests in multiple of sectors from the host system, which are then mapped to logical pages, the basic I/O units of the flash memory. As the SSD receives requests in sector units, the sectors in a logical page tend to exhibit diverse update frequencies. Therefore, frequent updates to some sectors of a page cause other sectors of the same page to be unnecessarily read and written to other free pages, thereby increasing write amplification and harming the flash memory lifetime. To eliminate unnecessary sector movement and to reduce write amplification, we propose a sector-level classification (SLC) technique. SLC considers the diversity in the update frequencies of sectors and merges sectors with similar update frequencies to generate full, homogeneous pages. Thus, multiple update operations can be converged to a single flash page, thereby reducing write amplification and increasing flash memory lifetime. SLC handles the merged sectors using the proposed shared-page mapping table (SMT), whereas pages whose sectors remain unmerged are handled by a conventional page mapping table. Despite the SMT overhead, SLC does not require excessive resources to accommodate SMT. The capability of SLC is evaluated by a series of experiments, which provides highly encouraging results. It is demonstrated that SLC reduces flash writes, flash reads, block erasures, and flash writes execution time by 42%, 23%, 45%, and 37%, respectively.

During the past decade, the endurance of NAND flash memory has severely deteriorated. The maximum number of program and erase cycles has fallen significantly with emerging of multilevel cell (MLC) and triple-level cell (TLC) technology, and scaling down of the cell size. Wear leveling is a general solution used to alleviate this issue; it enables cells to wear down evenly but it cannot actually mitigate the wearing of the cells. Accordingly, techniques are required to minimize the actual cell degradation. This paper proposesendurance-enhancing lower state encoding. The key insight leveraged by the proposed technique is the data pattern-related characteristic of MLC and TLC NAND flash memories, in which the lower the state of the cells, the lower the occurrence of wear out. Thus, our proposed scheme encodes input data to make the cell state as low as possible in consideration of interpage relation. As a result, the wear out of the memory cells can be minimized and their lifetime is improved by 62.7% in a file type and 43.0% in MySQL. Experimental results indicate that our scheme shows better lifetime improvement than other schemes in most cases.

The manufacturers of NAND flash-based solid-state drives (SSDs) are increasing capacity and throughput by enlarging their page size, which is the minimum I/O unit in the NAND flash chips. Because the host and NAND flash chips have different I/O granularity units, the number of subpage requests increases. However, these subpage requests, especially writes, can cause internal fragmentation and endurance problems. Furthermore, subpage write requests inevitably involve read-modify-write (RMW) operations that increase the write response time because of the out-place-update feature in the NAND flash chips. In this paper, we propose a subpage-aware SSD to increase the lifetime and performance by reducing the number of NAND writes and eliminating unnecessary RMW operations. Our scheme attempts to merge subpage write requests to full page write requests in the write buffer to reduce the number of NAND writes and adds size information to the mapping table to detect unnecessary RMW operations. Our proposed scheme reduces the number of NAND writes by up to 30 and 19 percent on average and the write response time by up to 22 and 13 percent on average.