High-density and reliable multilevel-cell (MLC) resistive random access memory (RRAM) is expected to meet the ever-increasing demand for on-chip weight storages in the intelligent edge devices. However, due to the device variations, many write-and-verify (WAV) iterations are usually required to program the RRAM cell, which causes high power consumption, long latency, and degradation on the memory lifetime. To address this issue, we propose a write–verify-free MLC RRAM macro for weight storage with 1) a cascode-current-mirror multibit write (CCM-MW) driver and 2) a nonbinary programming scheme (NB-PS) with a radix not greater than 2. A 180-nm 400-Kb RRAM test chip is demonstrated in silicon. For 2-bit-per-cell MLC storage, the value error rates can be reduced by 24.13% after introducing two redundant bits (RBDs). In addition, compared to the single-level cell (SLC) storage scheme, a 37.50% reduction in the number of cells can be achieved to store the ResNet-8 model with a 0.79% loss in inference accuracy without the need for WAV iterations.

In this article, a power-on-reset (POR) circuit with accurate trigger-point voltage and ultralow typical quiescent current for emerging nonvolatile memory (NVM) is presented. To keep the trigger-point voltage from the effect of process, voltage, and temperature (PVT) and supply ramp rate variations, low-cost current generators and a current comparator are adopted with brown-out detection (BOD). A protection circuit is utilized for correct operations in different BOD events. Meanwhile, delay blocks are utilized to generate reliable pulse signals that are less influenced by temperature and supply ramp rate. The simulation results show that the trigger-point voltage is 2.08 V with a temperature coefficient (TC) of 81.8 ppm/$^{\circ}$C and a deviation to the ramp time of 9.91% for a wide ramp time range from 10$\mu $s to dc. In addition, the reset duration time of the POR pulse is also reliable. The proposed POR circuit designed in the 55-nm CMOS process consumes only 0.65-nA typical quiescent current and 59$\times$146$\mu $m area, which is suitable for emerging NVM systems.

A 1.2~1.6 GHz low power single-ended input to differential output low noise amplifier for Global Navigation Satellite System (GNSS, such as GPS, Galileo, China Compass, etc.) is proposed in the paper. A new current-reused technique with mismatch adjustment is adopted to achieve low power, low noise factor, high voltage gain and low mismatch simultaneously. The LNA is fabricated in TSMC 0.18 μm RF CMOS process, with only 2 mA current consumption under 1.8 V supply. The LNA exhibits a differential voltage gain of 27-30 dB, a noise figure of 2.4-3.0 dB and gain mismatch less than 0.5 dB.

We report a ZrO2-based resistive memory composed of a thin Cu doped ZrO2layer sandwiched between Pt bottom and Cu top electrode. The Cu/ZrO2:Cu/Pt shows excellent nonpolar resistive switching behaviors, such as free-electroforming, high ON/OFF resistance ratio (106), fast Set/Reset speed (50 ns/100 ns), and reliable data retention (>10 years). The temperature-dependent switching characteristics show that a metallic filamentary channel is responsible for the low resistance state. Further analysis reveals that the physical origin of this metallic filament is the nanoscale Cu conductive filament. On this basis, we propose that the set process and the reset process stem from the electrochemical reactions in the filament, in which a thermal effect is greatly involved.