Memristor-based computation-in-memory (CiM) architectures address the growing computational demands of AI accelerators by enabling analog matrix-vector multiplication (MVM) directly within the memory array. Passive (selectorless) memristive crossbars are particularly attractive for such architectures due to their high density and compatibility with back-end-of-line fabrication. Here, AI model parameters are stored as memristor conductances, and MVM is performed in situ by activating multiple rows simultaneously and sensing the resulting column currents. As a result, column currents become the primary observable, making column-level fault detection more relevant for AI workloads than conventional March-based cell-level tests, which are specially time - and energy-intensive for passive crossbars due to specialized biasing methods. To address this, we propose a current-based testing methodology tailored to passive crossbars that detects and diagnoses faulty columns while accounting for non-idealities such as sneak-path currents, line resistance, and process variations. Faulty columns are detected by programming all cells to a uniform state and measuring column-current deviations, followed by targeted test patterns to estimate per-column fault density. On a $64 \times 64$ array, the proposed approach achieves 100% faulty column detection, 98% overall fault coverage, and a $2.3 \times$ speed-up in test time compared to conventional March tests. Hence, providing a fast and efficient solution for manufacturing screening of passive crossbars with sufficient diagnostic resolution to support systemlevel fault tolerance for AI applications.

The computation-in nonvolatile memory (NVM-CiM) approach addresses the growing computational demands and the memory-wall problem faced by traditional processor-centric architectures. Computation-in-memory (CiM) capitalizes on the parallel nature of memory arrays enabling effective computation through multirow memristor reading and sensing. In this context, the conventional design of memory decoders needs to be accordingly modified for efficient multirow activation and parallel data processing. This article presents the design and optimization of address decoders for NVM-CiM system architectures, employing a cross-layer co-optimization approach that integrates circuit and architecture design with application requirements. Our methodology starts at the circuit level, examining various decoder designs, including cascaded, hierarchical, latched, and hybrid models. An in-depth application-level characterization follows, utilizing an extended NVM-CiM-capable gem5 simulator to assess the impact of these decoders on the mapping of CiM-friendly applications and the resulting system performance, particularly in facilitating rapid and efficient activation of multirow memory configurations. This holistic analysis allows us to identify the bottlenecks and requirements from the application side and adjust the design of the decoder accordingly. Our analysis reveals that Hybrid Decoders significantly decrease latency and power consumption compared to other decoder designs within NVM-CiM systems. This highlights the crucial role of the decoder’s row selection flexibility, reducing additional system-level data movement even at the expense of its performance, can substantially improve the overall efficiency of NVM-CiM systems.