Yeongwoo Jang

dblp:392/3142 · DBLP profile ↗
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3ranked-venue papers
1as first author
3since 2021 · last 2026
0009-0004-6390-9112ORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Emerging computing paradigms · 29% Embedded and real-time systems · 20% Performance modeling and evaluation · 12%

Topics — the 10 heaviest of 12, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
neuromorphic computing
1.022025
Rearchitecting a Neuromorphic Processor for Spike-Driven Brain-Computer Interfacing · MICRO 2024
InfiniMind: A Learning-Optimized Large-Scale Brain-Computer Interface · ISCA 2025
Electronic design automation
design space exploration
1.012026
TierX: A Simulation Framework for Multi-tier BCI System Design Evaluation and Exploration · ASPLOS (2) 2026
Performance modeling and evaluation › simulation › simulation software
simulation framework
1.012026
TierX: A Simulation Framework for Multi-tier BCI System Design Evaluation and Exploration · ASPLOS (2) 2026
Hardware accelerators and domain-specific architectures › signal processing accelerator
brain-computer interface accelerator
0.912025
InfiniMind: A Learning-Optimized Large-Scale Brain-Computer Interface · ISCA 2025
Memory systems
non-volatile memory
0.912025
InfiniMind: A Learning-Optimized Large-Scale Brain-Computer Interface · ISCA 2025
Embedded and real-time systems
brain-computer interface
0.812024
Rearchitecting a Neuromorphic Processor for Spike-Driven Brain-Computer Interfacing · MICRO 2024
Emerging computing paradigms
event-driven computing
0.812024
Rearchitecting a Neuromorphic Processor for Spike-Driven Brain-Computer Interfacing · MICRO 2024
Emerging computing paradigms
neuromorphic hardware
0.812024
Rearchitecting a Neuromorphic Processor for Spike-Driven Brain-Computer Interfacing · MICRO 2024
GPUs and heterogeneous computing › heterogeneous computing systems
heterogeneous processing node
0.312026
TierX: A Simulation Framework for Multi-tier BCI System Design Evaluation and Exploration · ASPLOS (2) 2026
Parallel and multicore computing
task partitioning
0.312026
TierX: A Simulation Framework for Multi-tier BCI System Design Evaluation and Exploration · ASPLOS (2) 2026

Methods — techniques the papers use, named apart from their topics

simulation · 1.0waveform compression · 0.9update filtering · 0.9out-of-place flushing · 0.9delta buffering · 0.9multitask control · 0.8instruction set extension · 0.8custom synchronization · 0.8
YearPublicationVenuePosition
2026 TierX: A Simulation Framework for Multi-tier BCI System Design Evaluation and Exploration
abstract
Brain-computer interfaces (BCIs) have made remarkable progress in recent years, driven by advances in neuroscience and clinical applications. For practical use, underlying processing systems must meet strict latency and power budgets. However, existing BCI systems typically rely on a single processing node to handle the entire workload, making it difficult to satisfy these budgets across diverse applications. In this work, we present TierX, the first simulation framework for design space exploration of multi-tier BCI systems. TierX models heterogeneous processing nodes across tiers, including implanted processors, body-attached devices, and external servers, together with diverse communication and powering methods. It navigates the extensive design space to identify optimal (1) workload partitioning options and (2) system configurations that leverage the strengths of each tier. We validate TierX on representative system configurations and demonstrate its effectiveness across diverse use cases.
Seunghyun Song, Yeongwoo Jang, Daye Jung, Kyungsoo Park, Gwangjin Kim, Hunjun Lee, Jerald Yoo, Jangwoo Kim
ASPLOS (2)2
2025 InfiniMind: A Learning-Optimized Large-Scale Brain-Computer Interface
abstract
Brain-computer interfaces (BCIs) provide an interactive closed-loop connection between the brain and a computer.By employing signal processors implanted within the brain, BCIs are driving innovations across various fields in neuroscience and medicine.Recent studies highlight the need to integrate non-volatile memories (NVMs) into the implanted system for large-scale applications.At the same time, they emphasize the importance of continual learning within the system to address non-stationarities in the recorded signals.This work is the first to address the performance and lifetime issues of deploying learning on NVM-assisted BCI systems.To reduce excessive write overhead associated with learning support, we propose four optimization schemes tailored for BCI workloads.First, update filtering minimizes unnecessary writes by leveraging the sparse and recurring nature of BCI signals.Second, delta buffering exploits temporal locality inherent in BCI signals to minimize NVM writes.Third, out-of-place flushing reduces write amplification by packing multiple sub-page updates into a single page write.Fourth, waveform compression decreases the volume of written data by exploiting the structural characteristics of neural signals.We implement these optimizations in a memory controller and integrate it into the state-of-the-art NVM-assisted BCI system, realizing an endto-end learning-optimized system.Evaluation results show that our system improves performance and lifetime by 5.39× and 23.52×, respectively, on representative continual learning algorithms.
Yeongwoo Jang, Daye Jung, Seunghyun Song, Hunjun Lee, Jangwoo Kim
ISCA1
2024 Rearchitecting a Neuromorphic Processor for Spike-Driven Brain-Computer Interfacing
abstract
Brain-computer interfaces (BCIs) are electrophysiological devices (e.g., electrode arrays) that connect the brain to a computer. They offer neuroscientific and neurological innovations by utilizing a dedicated processor for continuous BCI signal processing. Recent studies propose a scaled-up BCI that adopts an order of magnitude larger number of electrodes to more precisely interface with the brain. As the BCI scales, utilizing a spike-driven processor emerges as an alternative processing method, where the BCI offloads computations to the processor upon detecting spikes. However, the processor design for spike-driven processing has been relatively unexplored compared to that of the continuous processor. In this work, we propose NeuroLobe, a flexible and efficient processor design for spike-driven processing. The key idea is to utilize a neuromorphic processor to take advantage of its event-driven computing nature. We carefully rearchitect the existing neuromorphic system for the purpose of flexibly and efficiently deploying the BCI algorithms. First, we extend the instruction set architecture of the existing neuromorphic processor to flexibly deploy representative spike-driven BCI algorithms. Second, we redesign the connection controller and execution path to improve the performance. Third, we design a custom synchronization unit for scalable processing. Fourth, we implement a custom software stack to minimize load imbalance among the cores. Lastly, we design a multitask controller to simultaneously process multiple algorithms. We evaluate NeuroLobe on four representative BCI algorithms with 11 configurations. Evaluation results show that NeuroLobe surpasses CPU and GPU in terms of speed and energy efficiency.
Hunjun Lee, Yeongwoo Jang, Daye Jung, Seunghyun Song, Jangwoo Kim
MICRO2