The memory wall is a major bottleneck for continuing to improve the energy efficiency of computing systems. To overcome this challenge, various nanomaterials, devices, circuits, architectures, and three-dimensional (3D) integration techniques are under development for future memory solutions. However, major trade-offs exist when designing memories to achieve high on-chip memory capacity, high retention time, high endurance, low access times, low access energy, and low static leakage power. We present an energy- and area-efficient embedded DRAM memory architecture (quantified by EADP: the product of total energy consumption, circuit area footprint and application execution time) that leverages monolithic threedimensional (3D) integration of three types of field-effect transistors (FETs): (i) Indium Gallium Zinc Oxide (IGZO) FETs for ultra-low off-state leakage currents enabling high retention time DRAM; (ii) Carbon Nanotube FETs (CNFETs) for high on-state drive currents leading to fast access times; and (iii) Silicon CMOS for its combined energy efficiency and low off-state leakage current (for memory peripheral circuits implemented on the bottom physical circuit layer). Our resulting 333-eDRAM achieves each of the following simultaneously, which we quantify and describe how to co-optimize in this paper: high density, high retention time, high endurance, low access times, low access energy, and low static leakage power. We show full physical layout designs detailing how to implement 333-eDRAM and quantify EADP for an ARM Cortex-M0 processor + on-chip 333-eDRAM implemented at a 7 nm technology node, running applications from the Embench benchmark suite. Using cycleaccurate simulations of applications, SPICE circuit simulations, compact models calibrated to experimental data, and detailed full physical layout designs of 333-eDRAM memories, we show that on average (across 16 Embench benchmarks), ARM CortexM0 + IGZO/CNT/Si 333-eDRAM offers $1.96 \times$ better EDP and $5.15 \times$ better EADP than ARM Cortex-M0 + Silicon eDRAM.

To address computing's carbon footprint challenge, designers of computing systems are beginning to consider carbon footprint as a first-class figure of merit, alongside conventional metrics such as power, performance, and area. To account for total carbon$(\text{tC})$footprint of a computing system, carbon footprint models must consider both embodied carbon$(\mathrm{C}_{\text{embodied}})$due to emissions during manufacturing, and operational carbon$(\mathbf{C}_{\text{operational}})$from day-to-day use. Models for$(\mathbf{C}_{\text{operational}})$are relatively mature due to the direct relationship between$(\mathbf{C}_{\text{operational}})$and energy consumed while computing. In contrast, models for$\mathrm{C}_{\text{embodied}}$primarily focus on today's silicon-based technologies, not capturing the wide range of beyond-Si technologies that are actively being developed for future computing systems, including emerging nanomaterials, emerging memory devices, and various three-dimensional (3D) integration techniques.$\mathbf{C}_{\text {embodied }}$models for emerging technologies are essential for accurately predicting which technology directions to pursue without exacerbating computing's carbon footprint. In this paper, we (1) develop$\mathbf{C}_{\text {embodied }}$models for$\mathbf{3D}$-integrated computing systems that leverage emerging nanotechnologies. We analyze an example fabrication process that is highly promising for energy-efficient computing:$3\mathbf{D}$integration of carbon nanotube field-effect transistors (CNFETs) and indium gallium zinc oxide (IGZO) FETs fabricated directly on top of Si CMOS at a 7 nm technology node. We show that$\mathbf{C}_{\text{embodied}}$of this process is, on average (considering various energy grids),$1.31\times$higher per wafer vs. a baseline 7 nm node Si CMOS process. (2) As a case study, we quantify tradeoffs in power, performance, area, and tC footprint for an embedded system comprising an ARM Cortex-M0 processor and embedded DRAM, implemented in each of the above processes. For a representative lifetime of the system (running applications from the Embench suite for 2 hours per day over 24 months, with a clock frequency of 500 MHz), we show that the 3D IGZO/CNFET/Si implementation is 1.02 × more carbon-efficient per good die (considering yield) vs. the baseline Si implementation, quantified by the product of tC and application execution time$(tCDP$, an effective metric of carbon efficiency). (3) Finally, we show techniques to quantify carbon efficiency benefits of future computing systems, even when there is uncertainty in carbon footprint models. Specifically, we show how to robustly compare$\text{tCDP}$for multiple computing systems, given underlying uncertainty in$\mathbf{C}_{\text{embodied}}$, computing system lifetime, carbon intensity (in equivalent grams of CO2emissions per unit energy consumption), and yield.

Photonic interposers are promising to advance energy-efficient clock tree distribution and high-bandwidth communication among chiplets. However, optimizing photonic interposer performance is challenging, since design tools for photonic integrated circuits (ICs) must account for all the following: (i) Optical timing skew among chiplets with arbitrary physical locations; (ii) Optical loss skew due to propagation and device loss; (iii) Routing/placement blockages for electronic-photonic systems; (iv) Detailed electronic-photonic circuit simulations to verify performance; (v) Physical verification (Design Rule Check, Layout Vs. Schematic) of photonic ICs; and (vi) Seamless integration with Electronic Design Automation (EDA) tools to facilitate electronic-photonic co-design. To address this challenge, we present: (1) Photonic-to-Electronic and Electronic-to-Photonic Integrated Circuit Transformations – we transform photonic ICs so they can be automatically designed and optimized using industry-standard EDA tools for electronic ICs (e.g., mapping optical propagation delays and losses into electrical RC wire delay within 5% accuracy, and transforming electrical IC layouts to photonic IC layouts). This enables us to leverage mature EDA tools to address all the above considerations simultaneously. To show the scalability of our approach, we automatically design a 128 × 128 electro-optical router in under 40 minutes. (2) Photonic interposer designs for Optical Clock Tree (OCT) distribution (we show example clock trees with up to 32 sinks) – compared to standalone design tools for OCT Synthesis, our approach improves optical timing skew by 13.85%. (3) Experimental demonstration of a photonic interposer, fabricated in Thin Film Lithium Niobate (TFLN), a promising material platform to realize high-bandwidth and low-loss photonic ICs – we experimentally measure optical loss skew of 2.16 dB among six OCT sinks on our photonic interposer. We also describe techniques to further reduce optical loss skew through electrical modulation of optical power.

Distributing a high-frequency clock signal across multiple chiplets in 2.5D integrated systems can be a challenging task due to the large physical distances among clock sinks. While silicon photonics can alleviate this challenge, conventional clock tree synthesis (CTS) algorithms that distribute an electrical clock signal cannot usefully consider the properties of light and the features of the photonic devices. These properties include the splitting of the optical power at the merging points and the effects induced by the analog receiver. A new bounded-skew synthesis methodology, targeting 2.5D integrated systems, is proposed, where an optical CTS (OCTS) algorithm determines the appropriate clock tree topology. The algorithm has as input the number and location of the photodetectors (effectively the clock sinks) and by utilizing 1 × 2, 1 × 3, and 1 × 5 splitters, the locations (loci) of the merging points are determined, such that the clock skew and power constraints are satisfied. The algorithm is applied on three benchmarks, utilizing LiNb technology, thereby demonstrating the effectiveness and generality of the approach compared to traditional CTS algorithms. For the explored benchmarks, the optical power losses are reduced up to 10.1% while bounding the skew to less than 10% of the clock period.