Demo Data from EDBT 2026 / reviewers in the wild / expert
Shunyu Mao
dblp:393/4319
· DBLP profile ↗
1ranked-venue papers
1as first author
1since 2021 · last 2025
0009-0007-6710-8066ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 67% Performance modeling and evaluation · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory interconnect
CXL |
0.9 | 1 | 2025 | CXL-INTERPLAY: Unraveling and Characterizing CXL Interference in Modern Computer Systems · DAC 2025 |
Memory systems
memory interconnect |
0.9 | 1 | 2025 | CXL-INTERPLAY: Unraveling and Characterizing CXL Interference in Modern Computer Systems · DAC 2025 |
Performance modeling and evaluation
workload characterization |
0.9 | 1 | 2025 | CXL-INTERPLAY: Unraveling and Characterizing CXL Interference in Modern Computer Systems · DAC 2025 |
Methods — techniques the papers use, named apart from their topics
reverse-reasoning analysis · 0.9performance counters · 0.9
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2025 | CXL-INTERPLAY: Unraveling and Characterizing CXL Interference in Modern Computer SystemsabstractCompute Express Link (CXL) is a promising technology that addresses memory and storage challenges. Despite its advantages, CXL faces performance threats from external interference when coexisting with current memory and storage systems. This interference is under-explored in existing research. To address this, we develop CXL-Interplay, systematically characterizing and analyzing interference from memory and storage systems. To the best of our knowledge, we are the first to characterize CXL interference on real CXL hardware. We also provide reverse-reasoning analysis with performance counters and kernel functions. In the end, we propose and evaluate mitigation solutions. Shunyu Mao, Jiajun Luo, Jiapeng Zhou, Zheng Liu 0022, Teng Ma 0006, Shuwen Deng |
DAC | 1 |