Demo Data from EDBT 2026 / reviewers in the wild / expert
Zhongchun Zheng
dblp:393/9414
· DBLP profile ↗
3ranked-venue papers
1as first author
3since 2021 · last 2026
0009-0002-8176-8486ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 1 first-author · 3 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Compilers and program optimization · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
GPUs and heterogeneous computing · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Compilers and program optimization › instruction scheduling
instruction-level parallelism |
0.9 | 1 | 2025 | GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving · DAC 2025 |
Compilers and program optimization
instruction scheduling |
0.9 | 1 | 2025 | GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving · DAC 2025 |
GPUs and heterogeneous computing
GPU kernel optimization |
0.9 | 1 | 2025 | GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving · DAC 2025 |
GPUs and heterogeneous computing › GPU kernel optimization
kernel fusion |
0.9 | 1 | 2025 | GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow Weaving · DAC 2025 |
Methods — techniques the papers use, named apart from their topics
control flow graph · 1.7PTX-level instruction weaving · 1.7
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | TensorAgent: Multi-agent Framework for Automated Tensor Core Code Generation
Zhongchun Zheng |
APPT | 2 |
| 2025 | GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow WeavingabstractGPUs have been heavily utilized in diverse applications, and numerous approaches, including kernel fusion, have been proposed to boost GPU efficiency through concurrent kernel execution. However, these approaches generally overlook the opportunities to mitigate warp stalls and improve instruction level parallelism (ILP) in inter-kernel resource sharing. To address this issue, we introduce GOPTX, a novel design for kernel fusion that improves ILP through deliberate weaving instructions at the PTX level. GOPTX establishes a merged control flow graph (CFG) from original kernels, enabling to interleaving of instructions that were sequentially executed by default and minimizing pipeline stalls on data hazards. We further propose a latency-aware instruction weaving algorithm for more efficient instruction scheduling and an adaptive code slicing method to enlarge the scheduling space. Experimental evaluation demonstrates that GOPTX achieves an average speedup of $\mathbf{1 1. 2 \%}$ over the baseline concurrent execution, with a maximum improvement of 23%. The hardware resource utilization statistics show significant enhancements in eligible warps per cycle and resource use. Zejia Lin 0001, Mengyue Xi, Zhongchun Zheng, Wenxuan Pan, Xianwei Zhang 0001, Yutong Lu |
DAC | 4 |
| 2024 | mLOOP: Optimize Loop Unrolling in Compilation with a ML-based ApproachabstractLoops are a fundamental component of programs, providing an structured and efficient way to execute repetitive tasks. Given their prevalence and significance, the performance of loops has a direct impact on the overall execution of a program. Predicting loop unroll factor holds remarkable importance in the domain of loop optimization and vectorization parallelism. With the rapid advancements in this field, leveraging machine learning (ML) methods for compilation optimization has emerged as a new research focus. Whereas traditional heuristic algorithms lack precision and Profile-Guided Optimization (PGO) techniques incur considerable compilation overhead, ML method serve as a more balanced approach with respect to accuracy and compilation time. Nonetheless, existing ML approaches are commonly confined to individual optimizations and fail to consider the interplay between multiple optimizations. Additionally, there is inadequate utilization of compilation optimization parameters, resulting in redundant calculations across different optimization processes. This paper proposes mLOOP, a method that employs the XGBoost model to predict loop unroll factors which are integrated into the metadata for use throughout the compilation pipeline. To facilitate deployment and testing in practices,$\text{mLOOP}$is encapsulated into a LLVM optimization pass. By testing on multiple loop-intensive benchmarks, mLOOP achieves 7% speedup on X86 platform and 12% on ARM. Zhongchun Zheng, Xianwei Zhang 0001 |
NAS | 1 |