Conventional architectures for the implementation of an algorithmic pattern generator (ALPG) are subject to practical limitations. The shared-resource ALPG utilizes common arithmetic operations across multiple input/output (I/O) pins, but its operating frequency is limited by the delay of arithmetic logic units (ALUs). In contrast, the per-pin ALPG achieves high-speed operations by generating one bit of the test vector for each I/O pin independently. However, the hardware area increases significantly since an individual pin pattern generator (PPG) is required for each I/O pin. To address these limitations, an area-efficient hybrid architecture for high-speed ALPG is proposed in this article. In the proposed hybrid ALPG, the lower bits of each test vector, where bit-level transitions occur frequently, are generated by a high-speed lower-bit pattern generator (LBPG), while the upper bits, where transitions are infrequent, are generated by a low-speed upper-bit pattern generator (UBPG). The maximum test rate of the proposed hybrid ALPG is determined by the high-speed LBPG, as it generates the lower bits that must be updated every test cycle. Consequently, the proposed hybrid architecture achieves high-speed ALPG while reducing the total hardware area, as the UBPG is designed with a simple structure, and the per-pin hardware resources in the LBPG are incorporated for only a limited number of I/O pins.

Scan-based testing is a widely used design for testability method to ensure the ease of testing. In this method, the enhanced observability and controllability provided by the inserted scan chains significantly improve the ability to analyze circuit data. However, since the enhanced testability can be exploited by malicious users as a backdoor for attacks, countermeasures need to be implemented to prevent scan chain access by unauthorized users. Although much research on secure scan designs has been conducted, most proposed methods are vulnerable to architecture exposure by reverse engineering. Moreover, even the latest proposed methods are affected by issues related to untrustworthy test engineers. This study proposes a pattern-sequence-authentication-based secure scan that not only defends against reverse engineering-based attacks but also prevents test engineers from launching attacks using additional patterns other than the given pattern. The proposed method effectively addresses the issue of secret key leakage through valid test patterns by untrustworthy test engineers, which is a limitation of the existing methods. The experimental results show that the proposed method effectively defends against existing attack techniques and ensures high security performance.

High-bandwidth memory (HBM) is one of the 3-D stacked memory standards that demonstrate high performance, including high bandwidth, large capacity, and low power consumption. However, despite these advantages, issues related to reliability and yield have imposed limitations on mass production. Various methodologies to enhance the reliability of HBM have been proposed, such as built-in self-repair (BISR) architectures and error correction code algorithms. Nevertheless, ensuring the reliability of through-silicon vias (TSV) remains a challenging problem. Existing built-in architectures aiming to enhance TSV reliability often incur significant hardware overhead, limiting practical applications. In this article, an innovative TSV BISR architecture that can detect and repair permanent TSV faults in real time at the user stage is proposed. The proposed architecture significantly enhances the reliability of HBM while implementing it with minimal hardware overhead. Furthermore, it effectively identifies both temporary errors and permanent TSV faults, enabling efficient TSV repairs. Through fast and accurate TSV fault repair, the proposed architecture substantially improves the reliability of HBM.

Errors emerge as a major issue in the reliability of dynamic random access memory (DRAM). To enhance reliability, a two-tiered error correction code (ECC) architecture that comprises on-die ECC (OD-ECC) and system ECC (S-ECC) is adopted as a part of the standard for state-of-the-art high-bandwidth memory (HBM). However, conventional ECCs are insufficient to mitigate malfunctions of subwordline drivers (SWDs), a primary cause of errors. Moreover, the efficient co-design of two-tiered ECCs has not been sufficiently studied. To address these issues without increasing the size of check bits, this article proposes a two-tiered ECC architecture comprising an OD-ECC based on prediction and an S-ECC with data deinterleaving. The proposed OD-ECC predicts the SWD errors by leveraging the detection capabilities of two interleaved Reed-Solomon (RS) engines. In addition, the proposed S-ECC not only preserves strong error detection capability but also masks the misprediction effect of OD-ECC, where data deinterleaving renders additional errors caused by misprediction of OD-ECC to be bounded in the detectable range of the employed cyclic redundancy check (CRC). The experimental results demonstrate that the proposed two-tiered ECC can significantly enhance the error correction capability for SWD errors while maintaining the correction capability for other types of errors.