Euijun Chung

dblp:394/7415 · DBLP profile ↗
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4ranked-venue papers
2as first author
4since 2021 · last 2026
0009-0002-7380-3552ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-author · 2 since 2021Software engineering, systems software and programming languages · 2 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Performance modeling and evaluation · 46% GPUs and heterogeneous computing · 30% Hardware reliability and fault tolerance · 23%
Network and information security
1 paper
Systems and software security · 100%

Topics — the 6 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Systems and software security
memory safety
0.912025
Let-Me-In: (Still) Employing In-pointer Bounds Metadata for Fine-grained GPU Memory Safety · HPCA 2025
Hardware reliability and fault tolerance
error modeling
0.912025
Swift and Trustworthy Large-Scale GPU Simulation with Fine-Grained Error Modeling and Hierarchical Clustering · MICRO 2025
GPUs and heterogeneous computing › GPU memory
GPU memory hierarchy
0.912025
Let-Me-In: (Still) Employing In-pointer Bounds Metadata for Fine-grained GPU Memory Safety · HPCA 2025
Performance modeling and evaluation › simulation › parallel architecture simulation
GPU simulation
0.912025
Swift and Trustworthy Large-Scale GPU Simulation with Fine-Grained Error Modeling and Hierarchical Clustering · MICRO 2025
Performance modeling and evaluation
simulation
0.912025
Swift and Trustworthy Large-Scale GPU Simulation with Fine-Grained Error Modeling and Hierarchical Clustering · MICRO 2025
GPUs and heterogeneous computing
GPU architecture
0.312025
Swift and Trustworthy Large-Scale GPU Simulation with Fine-Grained Error Modeling and Hierarchical Clustering · MICRO 2025

Methods — techniques the papers use, named apart from their topics

static analysis · 1.7pointer arithmetic marking · 1.7in-pointer bounds metadata · 1.7hierarchical clustering · 0.9fine-grained error modeling · 0.9
YearPublicationVenuePosition
2026 Macsim Mini: A Lightweight Cycle-Level GPU Simulator for Architecture Education
abstract
Cycle-level GPU simulators are valuable educational tools, but existing frameworks are either too complex for students to navigate or too abstract to convey microarchitectural details. We present Macsim Mini, a lightweight cycle-level GPU simulator designed for computer architecture education. By concentrating on the memory hierarchy and thread scheduling rather than detailed compute pipelines, Macsim Mini captures the architectural trade-offs most central to GPU performance in a codebase small enough for students to read and modify within course assignments. Macsim Mini has been deployed in a graduate-level GPU architecture and programming course for seven semesters, serving $\sim 1,000$ students with high completion rates and average scores above 90%.
Euijun Chung, Huanzhi Pu, Yuxiao Jia, Anurag Kar, Sam Jijina, Scott Madeira, Hyesoon Kim
ISPASS1
2026 TensorDynamic: Bridging Application- and Instruction-Level Fault Injection for DNN Tensor Core Execution
abstract
Deep neural network (DNN) inference relies heavily on Tensor Core operations, which are vulnerable to transient hardware faults in computation pipelines not protected by errorcorrecting codes (ECC). Prior fault injection work has explored both application-level and instruction-level effects on DNN accuracy. However, existing application-level approaches support only coarse perturbations and do not capture hardware execution details, while instruction-level approaches lack application-level context.To address this gap, we propose TensorDynamic, an application-aware instruction-level dynamic fault injection tool for Tensor Core execution in DNN workloads. TensorDynamic enables fine-grained fault injection into MMA (matrix-multiplyaccumulate) instructions during DNN execution. Across multiple models, we show that, under the same error injection rate and severity, application-level fault injection can produce substantially different inference outcomes from instruction-level fault injection. This result underscores the need for execution-aware fault injection when evaluating DNN resilience on GPU Tensor Cores.
Yuxiao Jia, Euijun Chung, Huanzhi Pu, Ben Feinberg, Hyesoon Kim
ISPASS2
2025 Let-Me-In: (Still) Employing In-pointer Bounds Metadata for Fine-grained GPU Memory Safety
abstract
The importance of ensuring the robustness of GPU systems has grown significantly, especially as GPUs have become vital in critical decision-making systems such as autonomous driving and medical diagnostics. However, GPU programming languages, primarily based on $\mathrm{C} / \mathrm{C}++$, inherit memory vulnerabilities that threaten the robustness of GPU applications. The heterogeneous GPU memory hierarchy makes it more difficult to find effective universal solutions. While several studies have proposed advanced GPU memory safety mechanisms, they still grapple with significant challenges, including substantial metadata storage and access overhead, elevated hardware implementation costs, and limited security coverage, particularly regarding fine-grained memory safety. We address this issue with Let-Me-In (LMI), a fine-grained memory safety mechanism specifically designed for GPUs. LMI features an efficient hardware bounds-checking mechanism that ensures negligible impact on performance and hardware costs, even in scenarios where thousands of concurrent threads perform memory operations across buffers in heap and local memory. This is achieved by aligning memory allocation to powers of two and performing static analysis to identify and mark pointer arithmetic instructions. This approach also enables storing metadata inside the unused upper bits of pointers, which are shrinking due to the expansion of the virtual memory address space. The unique characteristics of GPU programs make this approach feasible, unlike in CPU programs, where the inherent complexity of programs poses challenges. Our evaluation shows that LMI incurs only negligible hardware and performance overhead, making it a practical and efficient solution for enhancing GPU memory safety.
Euijun Chung, Seonjin Na, Yonghae Kim, Jaekyu Lee, Hyesoon Kim
HPCA2
2025 Swift and Trustworthy Large-Scale GPU Simulation with Fine-Grained Error Modeling and Hierarchical Clustering
Euijun Chung, Seonjin Na, Sung Ha Kang, Hyesoon Kim
MICRO1