Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Tayebeh Karimi

dblp:396/5452 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
1since 2021 · last 2025
0009-0007-7031-2244ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Emerging computing paradigms · 50% Integrated circuit design · 50%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design › digital circuit design › arithmetic circuit design
adder design
0.912025
Energy-Delay Efficient Segmented Approximate Adder With Smart Chaining · IEEE Trans. Computers 2025
Emerging computing paradigms › approximate computing › approximate circuit design › approximate arithmetic circuits
approximate adder
0.912025
Energy-Delay Efficient Segmented Approximate Adder With Smart Chaining · IEEE Trans. Computers 2025
Emerging computing paradigms
approximate computing
0.912025
Energy-Delay Efficient Segmented Approximate Adder With Smart Chaining · IEEE Trans. Computers 2025
Integrated circuit design
digital circuit design
0.912025
Energy-Delay Efficient Segmented Approximate Adder With Smart Chaining · IEEE Trans. Computers 2025
YearPublicationVenuePosition
2025 Energy-Delay Efficient Segmented Approximate Adder With Smart Chaining
abstract
Approximate computing is a promising approach for high-performance, and low-energy computation in inherently error-tolerant applications. This paper proposes an approximate adder comprising a constant-truncation block in the least significant part and several non-overlapping summation blocks in the more significant parts of the adder. The carry-in of each block is supplied using the most significant bit of one of the input operands from the earlier block. In the most significant block, two more-precise approaches are used to generate candidate values for the carry-in. The final value of the carry-in for this block is selected based on the values of the input operands. In fact, the proposed approximate adder is input-aware, and dynamically adjusts its operation in one or two cycles to improve accuracy while limiting the average delay. The experimental results indicate that the proposed adder has a better quality-effort tradeoff than state-of-the-art approximate adders. Different configurations of the proposed adder improve delay, energy, and the energy-delay product (EDP) by 78%, 72%, and 87%, respectively, when compared to state-of-the-art approximate adders, all without any loss in accuracy. Additionally, the efficiency of the proposed adder is confirmed in both image dithering and stock price prediction through regression.
Tayebeh Karimi, Arezoo Kamran
IEEE Trans. Computers1