Backside metal integration effectively mitigates IR-drop challenges, which become increasingly difficult to manage as CMOS technology scales down. However, compared to frontside-only chip designs, implementing backside metal incurs additional costs due to processes such as wafer thinning and nTSV formulation. To maximize the advantages of backside integration, the industry is now exploring functional backside technology. This article introduces a novel BS-PDN-last flow that is critical for the multifunctional utilization of backside metal layers. The BS-PDN-last flow defers Power/Ground (P/G) routing to a later stage of the physical design process, in contrast to the conventional approach where it is performed early in the flow. As a result, BS-PDN-last overcomes the voltage drop and performance trade-offs inherent in conventional flows, enabling substantial performance gains while maintaining low IR-drop levels. Experimental results show that the BS-PDN-last flow achieves a 90% reduction in Total Negative Slack and a 12% performance gain with Backside Clock Delivery Network.

The increasing demand to maximize PPA gains with backside metal layers has driven their function beyond power delivery. This study introduces a novel BS-PDN-last flow, crucial for leveraging multifunctional backside, by deferring power routing to the post-signal routing stage. This approach addresses the IR-drop and performance trade-offs inherent in conventional PDN-first flows. Experimental results show that the BS-PDN-last flow achieves a $90 \%$ reduction in Total Negative Slack and a $\mathbf{1 2 \%}$ performance gain with BS-CDN. Additionally, our work presents the first comprehensive comparison of FS-PDN, BSPDN, and multifunctional backside designs, evaluated on both physical design and workload metrics leveraging accurate vector-based analysis.

Gate-level 3D ICs have demonstrated substantial power and performance improvements over 2D ICs. However, at advanced technology nodes, achieving sufficient hybrid bond density within a reduced chip footprint requires a 200nm bond pitch—beyond the limits of current manufacturing capabilities. To address this issue, we focus on block-level 3D IC design which has fewer top-level connections. Previous methodologies for block-level 3D IC design suffer from several limitations: (1) reliance on slow simulated annealing-based floorplanning, (2) suboptimal 3D design flows lacking post-route optimization, (3) a lack of attention to the critical initial step of soft block design, and (4) excessive hybrid bond usage that necessitates a 500nm pitch. To overcome these challenges, we propose a comprehensive methodology that includes: (1) a fast, gradient-based analytical solver, (2) Fence-3D flow, delivering up to 15% improvement in power-delay product, (3) ML-based congestion-aware soft block sizing, delivering up to 6.6% improvement, and (4) a partial-MLS method that selectively applies Metal Layer Sharing, reducing hybrid bond count by up to 71%. Collectively, these techniques enable the use of a 1um hybrid bond pitch in 3nm block-level 3D ICs.

3D Integrated Circuits (ICs) significantly enhance chip performance but require substantial engineering due to their expanded design space. To tackle this, we introduce the MIX-3D framework, an advanced optimizer utilizing Variational Autoencoders for robust extrapolation, identifying energy-efficient and thermal-aware design configurations for mixed-node, mixed-area 3D ICs. It enables architecture-circuit co-design for F2F 2-tier Logic-on-Memory 3D ICs, providing real-time predictions of both back-end and front-end metrics. Additionally, transfer learning reduces dataset construction time by 64%, a common challenge in supervised learning. Experimental results demonstrate that MIX-3D delivers 12% improvements in energy efficiency and 62% less power compared to equal-area 3D ICs. Furthermore, our thermal-aware design reduces chip temperature by 38%.

This article presents 3DNN-Xplorer, the first machine learning (ML)-based framework for predicting the performance of heterogeneous 3-D deep neural network (DNN) accelerators. Our ML framework facilitates the design space exploration (DSE) of heterogeneous 3-D accelerators with a two-tier compute-on-memory (CoM) configuration, considering 3-D physical design factors. Our design space encompasses four distinct heterogeneous 3-D integration styles, combining 28- and 16-nm technology nodes for both compute and memory tiers. Using extrapolation techniques with ML models trained on 10-to-256 processing element (PE) accelerator configurations, we estimate the performance of systems featuring 75–16384 PEs, achieving a maximum absolute error of 13.9% (the number of PEs is not continuous and varies based on the accelerator architecture). To ensure balanced tier areas in the design, our framework assumes the same number of PEs or on-chip memory capacity across the four integration styles, accounting for area imbalance resulting from different technology nodes. Our analysis reveals that the heterogeneous 3-D style with 28-nm compute and 16-nm memory is energy-efficient and offers notable energy savings of up to 50% and an 8.8% reduction in runtime compared to other 3-D integration styles with the same number of PEs. Similarly, the heterogeneous 3-D style with 16-nm compute and 28-nm memory is area-efficient and shows up to 8.3% runtime reduction compared to other 3-D styles with the same on-chip memory capacity.