This paper proposes an uncertainty quantification (UQ)-incorporated design optimization technique that integrates UQ considering the statistical characteristics of sensing margin with machine learning (ML) for the design of bitline sense amplifiers (BLSAs) in dynamic random access memory (DRAM), including offset compensation operation. The increased offset due to process variation exacerbated by device scaling degrades the reliability of DRAM read operations, making quantitative analysis of process variation essential. Conventional Monte Carlo (MC)-based UQ analysis provides high accuracy but requires extensive simulation costs. Accordingly, this study systematically defines key input and output variables for conventional BLSA and two representative offset compensation BLSA structures, introduces Sobol sequence-based quasi-Monte Carlo (QMC) sampling to improve simulation efficiency, and generalizes the Standard UQ methodology to predict statistical distributions of circuit performance parameters under process variation. Furthermore, a 3-Stage UQ algorithm that sequentially learns nominal, mean, and standard deviation values is proposed to enhance the efficiency of ML model training. HSPICE simulation results based on the TSMC 65 nm process demonstrated that the proposed 3-Stage UQ method reduced the simulation time required for ML training data generation by an average of 43% compared to the Standard UQ method and achieved excellent prediction performance even in data-limited environments. Additionally, design optimization combined with Bayesian Optimization (BO) confirmed performance improvements across all circuit structures. The methodology presented in this study enables effective process variation-aware optimization for DRAM designs requiring high reliability and yield, and is expected to contribute to next-generation memory circuit design automation.