This paper presents a single-ended four-level pulse amplitude modulation (PAM-4) receiver for memory interfaces. The front-end employs a T-coil, an inverter-based hybrid continuous-time linear equalizer (CTLE), and a decision-feedback equalizer (DFE) to compensate for complex channel losses. Additionally, a cross-coupled pair (XCP) is incorporated to enhance the single-to-differential (S2D) conversion performance of the CTLE, which results in improved differential-mode gain. Unlike conventional current-mode DFE implementations, the proposed DFE employs voltage-feedback using resistive digital-to-analog converters (DACs), source followers (SFs), and voltage multiplexers (VMUXes) to ensure robust operation. To verify the capability of the proposed single-ended PAM-4 receiver, a prototype is fabricated using 40-nm CMOS technology, occupying an active area of 0.039 mm${}^{\mathbf {2}}$. The 36 Gb/s single-ended PAM-4 receiver achieves a bit error rate (BER) below 10${}^{\mathbf {-12}}$over a channel exhibiting 11.71 dB insertion loss at 9 GHz. The receiver consumes 51.89 mW, achieving an energy efficiency of 1.44 pJ/bit.

This paper presents a 56-Gb/s 3-tap feed-forward equalizer (FFE) four-level pulse-amplitude modulation (PAM-4) transmitter (TX) frontend for wireline applications. The proposed transmitter frontend operates at a 0.85-V termination voltage utilizing external surface-mounted (SMT) bias-tees. Unlike conventional tail-less current-mode logic (CML) drivers with variable gate biases, the transmitter frontend employs shunt-FFE for fewer variations in output common-mode levels. The design is fabricated in 40-nm CMOS technology and occupies 0.021 mm2. The proposed PAM-4 transmitter design operating at 56 Gb/s consumes 22.0 mW from 0.85-V supply voltage, achieving 0.39-pJ/bit energy efficiency.

This article presents an automatic layout generation framework in advanced CMOS technologies. The framework extends the template-and-grid-based layout generation methodology to produce optimal layouts more efficiently. Layout templates and grids are dynamically created and adjusted during the generation phase to provide more reusability and flexibility. Virtual instances are used to encapsulate the dynamically generated layout structures. Internal node probes embedded in the dynamic templates capture parasitic effects precisely. The framework also implements various post-processing functions to handle process-specific tasks while maintaining the overall process portability of procedural layout generators. The post-processing functions include cut/dummy pattern generation and multiple-patterning adjustment. The generator description coverage is enhanced with circular grid indexing/slicing and conditional conversion operators. The layout generation framework is applied to generate various DRC/LVS clean layouts automatically in advanced CMOS technologies, achieving 0.66–249.35 transistors-per-line (the ratio of the generated transistor count to the source lines of code) generation efficiencies.