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Tianjun Bu

dblp:398/4836 · DBLP profile ↗
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3ranked-venue papers
0as first author
3since 2021 · last 2025
0009-0009-7016-4266ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Software engineering, systems software and programming languages · 2 · 2 since 2021Theory of computation · 2 · 2 since 2021Systems, architecture and hardware · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Theoretical computer science
2 papers
Automated reasoning and model checking · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Automated reasoning and model checking
model checking
1.722025
Deeply Optimizing the SAT Solver for the IC3 Algorithm · CAV (1) 2025
The rIC3 Hardware Model Checker · CAV (1) 2025
Automated reasoning and model checking › model checking
property directed reachability
1.722025
Deeply Optimizing the SAT Solver for the IC3 Algorithm · CAV (1) 2025
The rIC3 Hardware Model Checker · CAV (1) 2025
Electronic design automation › hardware verification and test
hardware verification
0.912025
The rIC3 Hardware Model Checker · CAV (1) 2025
Automated reasoning and model checking › satisfiability › SAT solving
conflict-driven clause learning
0.912025
Deeply Optimizing the SAT Solver for the IC3 Algorithm · CAV (1) 2025
Automated reasoning and model checking › model checking
hardware model checking
0.912025
The rIC3 Hardware Model Checker · CAV (1) 2025
Automated reasoning and model checking › satisfiability
SAT solving
0.912025
Deeply Optimizing the SAT Solver for the IC3 Algorithm · CAV (1) 2025

Methods — techniques the papers use, named apart from their topics

SAT solving · 1.7IC3 · 1.7VSIDS · 0.9CDCL · 0.9
YearPublicationVenuePosition
2025 The rIC3 Hardware Model Checker
abstract
Abstract In this paper, we present rIC3, an efficient bit-level hardware model checker primarily based on the IC3 algorithm. It boasts a highly efficient implementation and integrates several recently proposed optimizations, such as the specifically optimized SAT solver, dynamically adjustment of generalization strategies, and the use of predicates with internal signals, among others. As a first-time participant in the Hardware Model Checking Competition, rIC3 was independently evaluated as the best-performing tool, not only in the bit-level track but also in the word-level bit-vector track through bit-blasting. Our experiments further demonstrate significant advancements in both efficiency and scalability. rIC3 can also serve as a backend for verifying industrial RTL designs using SymbiYosys. Additionally, the source code of rIC3 is highly modular, with the IC3 algorithm module being particularly concise, making it an academic platform that is easy to modify and extend.
Yuheng Su, Qiusong Yang, Yiwei Ci, Tianjun Bu
CAV (1)4
2025 Deeply Optimizing the SAT Solver for the IC3 Algorithm
abstract
Abstract The IC3 algorithm, also known as PDR, is a SAT-based model checking algorithm that has significantly influenced the field in recent years due to its efficiency, scalability, and completeness. It utilizes SAT solvers to solve a series of SAT queries associated with relative induction. In this paper, we introduce several optimizations for the SAT solver in IC3 based on our observations of the unique characteristics of these SAT queries. By observing that SAT queries do not necessarily require decisions on all variables, we compute a subset of variables that need to be decided before each solving process while ensuring that the result remains unaffected. Additionally, noting that the overhead of binary heap operations in VSIDS is non-negligible, we replace the binary heap with buckets to achieve constant-time operations. Furthermore, we support temporary clauses without the need to allocate a new activation variable for each solving process, thereby eliminating the need to reset solvers. We developed a novel lightweight CDCL SAT solver, GipSAT, which integrates these optimizations. A comprehensive evaluation highlights the performance improvements achieved by GipSAT. Specifically, the GipSAT-based IC3 demonstrates an average speedup of $$3.61$$ 3.61 times in solving time compared to the IC3 implementation based on MiniSat.
Yuheng Su, Qiusong Yang, Yiwei Ci, Yingcheng Li, Tianjun Bu
CAV (1)5
2025 Fast, Transparent and Accurate Simulation of Thousand Processing-in-Memory Cores
Zhichao Lv, Tianjun Bu, Qiusong Yang
ACM Great Lakes Symposium on VLSI2