Placement plays a crucial role in modern chip design, aiming to determine the positions of circuit blocks (macros and standard cells). Traditional data structure-centric heuristics often yield suboptimal placement prototypes, ineffectively guiding downstream mixed-size analytical placement to find the desired results for modern large-scale designs. Recent works have showcased the potential of reinforcement learning (RL) to enhance chip placement by training a policy to place macros as a board game. However, placing macros and fixing them in the earlier stages without sufficient information often incurs undesired solutions. This paper proposes a novel RL-based mixed-size placer with iteratively moving the blocks to characterize dense rewards and comprehensive layout information in each step. We further introduce a semi-concurrent moving mechanism to learn the collaborative dynamics among actions on a subset of blocks at each step. We integrate continuous action spaces to develop a deep Q network-based model for learning the semi-concurrent moving policy to derive the proposed moving strategy. Compared with the state-of-the-art methods, experimental results show that our RL-based placer achieves the best placement quality based on commonly used mixed-size placement benchmarks.

IR drop analysis in the power delivery network (PDN) is crucial for the signoff of integrated circuit (IC) design. Static IR drop significantly affects the IC reliability. Machine learning (ML) has recently been applied to static IR drop prediction for its high accuracy and efficiency. However, most previous works cannot predict with unseen designs, and none can handle different technologies. These problems lead to long training times and data-gathering difficulties, making ML-based methods impractical in the industry. Therefore, a more applicable methodology for static IR drop predictions is needed. This paper proposes a fast, robust, highly technology-transferable image-to-image ML-based methodology for static IR-drop prediction. To enhance transferability and accuracy, we introduce a new input feature, layerwise maps, which encapsulates the PDN network topology well. We further derive a novel generic ML model for various designs and technologies with different numbers of PDN layers. Experimental results demonstrate our methodology's high accuracy, robustness, and technology transferability. We used only ten circuits to tune our pre-trained model on a new technology and achieved an average error rate of 10.4% IR drop value on unseen circuits. Additionally, we tuned our pre-trained model for the 2023 ICCAD CAD Contest. Compared to the contest winner, our method gets a comparable average error rate of 0.000152mV with a run time of less than 1.5 seconds and improves the MAE of the worst case by 29.7%.

Global routing is a critical stage in the VLSI design flow, aiming to provide a robust guide for detailed routing and serve as early design feedback for placement. Many approaches have leveraged GPU parallelization to achieve significant acceleration. However, with the fast-growing complexity of modern large-scale designs, recent GPU-accelerated maze routing algorithms, driven by the sweep operation, struggle to find solutions efficiently with limited GPU memory resources. In order to address this issue, this paper proposes a scalable, GPU-friendly sweep-based maze routing that requires significantly less memory and fewer kernel function calls while accelerating overall runtime. We introduce a sweep-sharing technique that allows multiple nets to be routed simultaneously within a single sweeping process, substantially reducing memory consumption and kernel launching overhead. We further propose an edge-level rip-up-andreroute technique that selectively reroutes only overflowed segments, preserving feasible parts of the solution to reduce runtime substantially. Experimental results on the latest ISPD’24 Contest benchmarks demonstrate that our GPUfriendly maze routing with sweep sharing can significantly improve the efficiency of the state-of-the-art GPU-accelerated maze router.