Demo Data from EDBT 2026 / reviewers in the wild / expert
Jen-Cheng Huang
dblp:40/10369
· DBLP profile ↗
6ranked-venue papers
4as first author
0since 2021 · last 2017
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 3 first-authorComputer networks · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 91% GPUs and heterogeneous computing · 9% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation › processor performance modeling › accelerator performance modeling
GPU performance modeling |
0.2 | 1 | 2014 | GPUMech: GPU Performance Modeling Technique Based on Interval Analysis · MICRO 2014 |
Performance modeling and evaluation › numerical algorithms
interval analysis |
0.2 | 1 | 2014 | GPUMech: GPU Performance Modeling Technique Based on Interval Analysis · MICRO 2014 |
Performance modeling and evaluation
simulation |
0.2 | 1 | 2014 | GPUMech: GPU Performance Modeling Technique Based on Interval Analysis · MICRO 2014 |
GPUs and heterogeneous computing
GPU architecture |
0.1 | 1 | 2014 | GPUMech: GPU Performance Modeling Technique Based on Interval Analysis · MICRO 2014 |
Methods — techniques the papers use, named apart from their topics
interval analysis · 0.2functional simulation · 0.2CPI stack generation · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2017 | SimProf: A Sampling Framework for Data Analytic WorkloadsabstractToday, there is a steep rise in the amount of data being collected from diverse applications. Consequently, data analytic workloads are gaining popularity to gain insight that can benefit the application, e.g., financial trading, social media analysis. To study the architectural behavior of the workloads, architectural simulation is one of the most common approaches. However, because of the long-running nature of the workloads, it is not trivial to identify which parts of the analysis to simulate. In the current work, we introduce SimProf, a sampling framework for data analytic workloads. Using this tool, we are able to select representative simulation points based on the phase behavior of the analysis at a method level granularity. This provides a better understanding of the simulation point and also reduces the simulation time for different input sets. We present the framework for Apache Hadoop and Apache Spark frameworks, which can be easily extended to other data analytic workloads. Jen-Cheng Huang, Lifeng Nai, Pranith Kumar, Hyojong Kim, Hyesoon Kim |
IPDPS | 1 |
| 2014 | ATAC: Ambient Temperature-Aware Capping for Power Efficient DatacentersabstractThe emergence of cloud computing has created a demand for more datacenters, which in turn, has led to the substantial consumption of electricity by computing systems and cooling units. Although recently built warehouse-scale datacenters can nearly completely eliminate cooling overhead, small to medium datacenters, which still spend nearly half of their power on cooling, still labor under heavy cooling overhead. Often overlooked by the cloud computing community, these types of datacenters are not in the minority: They are responsible for more than 70% of the entire electrical power used by datacenters. Thus, to tackle the cooling inefficiencies of these datacenters, we propose ambient temperature-aware capping (ATAC), which maximizes power efficiency while minimizing overheating. ATAC senses the ambient temperature of each server and triggers a new performance capping mechanism to achieve 38% savings in cooling power and 7% savings in total power with less than 1% degradation in performance. Sungkap Yeo, Mohammad M. Hossain, Jen-Cheng Huang, Hsien-Hsin S. Lee |
SoCC | 3 |
| 2014 | TBPoint: Reducing Simulation Time for Large-Scale GPGPU KernelsabstractArchitecture simulation for GPGPU kernels can take a significant amount of time, especially for large-scale GPGPU kernels. This paper presents TBPoint, an infrastructure based on profiling-based sampling for GPGPU kernels to reduce the cycle-level simulation time. Compared to existing approaches, TBPoint provides a flexible and architecture-independent way to take samples. For the evaluated 12 kernels, the geometric means of sampling errors of TBPoint, Ideal-Simpoint, and random sampling are 0.47%, 1.74%, and 7.95%, respectively, while the geometric means of the total sample size of TBPoint, Ideal-Simpoint, and random sampling are 2.6%, 5.4%, and 10%, respectively. TBPoint narrows the speed gap between hardware and GPGPU simulators, enabling more and more large-scale GPGPU kernels to be analyzed using detailed timing simulations. Jen-Cheng Huang, Lifeng Nai, Hyesoon Kim, Hsien-Hsin S. Lee |
IPDPS | 1 |
| 2014 | GPUMech: GPU Performance Modeling Technique Based on Interval AnalysisabstractGPU has become a first-order computing plat-form. Nonetheless, not many performance modeling techniques have been developed for architecture studies. Several GPU analytical performance models have been proposed, but they mostly target application optimizations rather than the study of different architecture design options. Interval analysis is a relatively accurate performance modeling technique, which traverses the instruction trace and uses functional simulators, e.g., Cache simulator, to track the stall events that cause performance loss. It shows hundred times of speedup compared to detailed timing simulations and better accuracy compared to pure analytical models. However, previous techniques are limited to CPUs and not applicable to multithreaded architectures. In this work, we propose GPU Mech, an interval analysis-based performance modeling technique for GPU architectures. GPU Mech models multithreading and resource contentions caused by memory divergence. We compare GPU Mech with a detailed timing simulator and show that on average, GPU Mechhas 13.2% error for modeling the round-robin scheduling policy and 14.0% error for modeling the greedy-then-oldest policy while achieving a 97x faster simulation speed. In addition, GPU Mech generates CPI stacks, which help hardware/software developers to visualize performance bottlenecks of a kernel. Jen-Cheng Huang, Joo Hwan Lee, Hyesoon Kim, Hsien-Hsin S. Lee |
MICRO | 1 |
| 2012 | Migration energy-aware workload consolidation in enterprise cloudsabstractConsolidation through live VM migrations is a promising approach to improve server utilization. However, prior consolidation works have focused mostly on the performance impact of migration and neglected the associated energy overhead. Our research finds that energy impact of migration can offset over 12 % of the energy saved through energy-conscious workload packing. To address this limitation of the current state of research, in this paper we devise new schemes to pack applications that targets a joint optimization of energy and performance overhead of VM migrations. Additionally, we develop a statistical workload modeling technique for simulating consolidation problem in enterprise cloud contexts. Our experiments with statistically generated synthetic trace and Google's production trace demonstrate that our schemes can improve energy savings up to 23% compared to state of the art power-aware workload consolidation strategy. Mohammad M. Hossain, Jen-Cheng Huang, Hsien-Hsin S. Lee |
CloudCom | 2 |
| 2011 | Ally: OS-Transparent Packet Inspection Using Sequestered CoresabstractThis paper presents Ally, a server platform architecture that supports compute-intensive management services on multi-core processors. Ally introduces simple hardware mechanisms to sequester cores to run a separate software environment dedicated to management tasks, including packet processing software appliances (e.g. for Deep Packet Inspection, DPI) with efficient mechanisms to safely and transparently intercept network packets. Ally enables distributed deployment of compute-intensive management services throughout a data center. Importantly, it uniquely allows these services to be deployed independent of the arbitrary OSs and/or hyper visor that users may choose to run on the remaining cores, with hardware isolation preventing the host environment from tampering with the management environment. Experiments using full system emulation and a Linux-based prototype validate Ally functionality and demonstrate low overhead packet interception, e.g., using Ally to host the well-known Snort packet inspection software incurs less over-head than deploying Snort as a Xen virtual machine appliance, resulting in up to 2× improvement in throughput for some workloads. Jen-Cheng Huang, Matteo Monchiero, Yoshio Turner, Hsien-Hsin S. Lee |
ANCS | 1 |