This paper analyses the sensitivity of the pMOS Wheatstone bridge stress sensors in 180-nm CMOS process. Other reported works use coarser process nodes. The pMOS sensors have a maximum or minimum sensitivity to the in-plane normal stress components for different orientations of the bridge arms with respect to the wafer coordinate system. The experimental results show that the sensors oriented orthogonally to the wafer axes have an absolute sensitivity of around 400 µV/MPa, while the absolute sensitivity of the diagonally oriented sensors is around 3 µV/MPa. The temperature measurements show low temperature dependency. The sensitivity to stress changes around −3% at 5 °C and around +1% at 50 °C, with respect to 25 °C.

This paper presents a stress-dependent MOSFET model which is valid from strong to weak inversion, based on the extension of the previous model that covers only the operation in strong inversion. The presented model operates for any MOSFET model type since it does not depend on model parameters. It can be used to simulate complex circuits and compensate for the effects caused by mechanical stress. Mechanical stress is caused by IC packaging and can potentially bring the circuits out of specifications, but stress-aware device models are not standard in circuit simulators which limits the ability to simulate these effects. A measurement method is presented and used to calibrate and validate the models.

In this work, the design methodology of the relaxation oscillator with the post-processing trimming option for frequency and temperature coefficient is presented. A novel oscillator core is introduced, which ensures good control linearity and insensitivity to CMOS variations of the output frequency as a prerequisite for frequency and temperature calibration. The proposed oscillator operates at 2 MHz and consumes typically about$I_{DD}=97.8\,\,\mu \text{A}$at the nominal temperature of 42.5°C and nominal supply voltage of$V_{DD}=1.8$V. The oscillator is verified experimentally with 10 samples manufactured in 180 nm CMOS process, each covering an area of 0.075 mm2. The frequency and temperature calibration was performed based on the two-point temperature measurements, resulting in a significant improvement in frequency stability. The temperature calibrated oscillator has a temperature variation ±0.30% in the temperature range from −40°C to 125°C, and the variation with the power supply ±0.07% in the supply range from 1.62 V to 1.98 V.

An improved relaxation oscillator core is designed and fabricated in 0.35-μm CMOS process, occupying the area of 0.032 mm2and consuming around 160 μW while running at 1 MHz. Employing a self-compensating chopped comparator structure, the designed oscillator exhibits the improvement in the frequency stability, at the same time retaining a fast start-up and having a minimal overhead in the power consumption and area. Measured on 9 test chips, the frequency variation against temperature is ±0.26% in the temperature range from -40 to 125 °C, and the line sensitivity is 0.16 %/V with the supply voltage changing from 3.0 to 4.5 V.