Demo Data from EDBT 2026 / reviewers in the wild / expert
Youngjo Jang
dblp:40/1464
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Graphics, computer vision, multimedia, augmented reality and games · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 67% Parallel and multicore computing · 33% |
Topics — the 3 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › physical design
floorplanning |
0.0 | 1 | 1991 | Stepwise-overlapped parallel annealing and its application to floorplan designs · Comput. Aided Des. 1991 |
Parallel and multicore computing › parallel algorithms › parallel combinatorial optimization
parallel simulated annealing |
0.0 | 1 | 1991 | Stepwise-overlapped parallel annealing and its application to floorplan designs · Comput. Aided Des. 1991 |
Electronic design automation
physical design |
0.0 | 1 | 1991 | Stepwise-overlapped parallel annealing and its application to floorplan designs · Comput. Aided Des. 1991 |
Methods — techniques the papers use, named apart from their topics
simulated annealing · 0.0genetic algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1991 | Stepwise-overlapped parallel annealing and its application to floorplan designsabstractA new parallel annealing scheme, stepwise-overlapped parallel annealing, is proposed. This can provide a massive speedup using a multiprocessor system with a large number of processors. It decomposes the annealing process by means of Markov chains. The annealing scheme of the systolic algorithm proposed by Aart et al. is improved. The improved annealing schedule keeps a good temperature profile even when a large number of processors are used. The communication pattern is also enhanced. The new parallel annealing algorithm is applied to floorplan design problems. Experimental results show that the new parallel annealing algorithm is highly effective for a large number of processors. The experimental results of the proposed algorithm are compared with those of other parallel annealing algorithms and the distributed genetic algorithm. Youngtak Kim, Youngjo Jang, Myunghwan Kim 0001 |
Comput. Aided Des. | 2 |