Ising problem is an NP-hard combinatorial op-timization problem. Recently, networks of mutually coupled, nonlinear, self-sustaining oscillators known as Oscillator Ising Machines (OIMs) were shown to heuristically solve Ising prob-lems. The phases of the oscillators in OIMs can be modeled as systems of Ordinary Differential Equations (ODEs) known as Generalized Kuramoto (Gen-K) models. In this paper, we solve Gen-K Ode systems efficiently using cleverly designed fixed point operations. To demonstrate this idea, we fabricated a prototype chip containing 33 spins with programmable all-to-all connectivity. We test this design using Multi-Input Multi-Output decoding problems, and show that the OIM emulator achieves near-optimal Symbol Error Rates (SER).

Over the last several years, Oscillator Ising Machines (OIMs) have been shown to heuristically solve NP-hard combinatorial optimization (CO) problems, most notably MAX-CUT. In this paper, we show that OIMs are capable of solving Multi-User Multiple-Input-Multiple-Output (MU-MIMO) detection, an important real-world problem in telecommunications, achieving near-optimal Symbol Error Rates (SERs). Our results are obtained using CPU- and GPU-based simulation; the latter features a parallelizable event-based algorithm for the generalized Kuramoto equations that reduces OIM simulation times by about 6× without losing accuracy. We also find that good SER results are obtained if 6 or more bits are used to quantize the Ising problem's coupling weights. We provide runtime, throughput and energy consumption comparisons of different implementations and algorithms for MU-MIMO detection, including an OIM emulator chip we had reported earlier. Our results provide useful guidance for designing analog OIM ICs tailored for MU-MIMO detection.

Almost all practical systems rely heavily on physical parameters. As a result, parameter sensitivity, or the extent to which perturbations in parameter values affect the state of a system, is intrinsically connected to system design and optimization. We present TADsens, a method for computing the parameter sensitivities of an output of a differential algebraic equation (DAE) system. Specifically, we provide rigorous, insightful theory for adjoint sensitivity computation of DAEs, along with an efficient and numerically well-posed algorithm implemented in Berkeley MAPP. Our theory and implementation advances resolve longstanding issues that have impeded adoption of adjoint transient sensitivities in circuit simulators for over 5 decades. We present results and comparisons on two nonlinear analog circuits. TADsens is numerically well posed and accurate, and faster by a factor of 300 over direct sensitivity computation on a circuit with over 150 unknowns and 600 parameters.

Ising machines have generated much excitement in recent years due to their promise for solving hard combinatorial optimization problems. However, achieving physical all-to-all connectivity in IC implementations of large, densely-connected Ising machines remains a key challenge. We present a novel approach, DaS, that uses low-rank decomposition to achieve effectively-dense Ising connectivity using only sparsely interconnected hardware. The innovation consists of two components. First, we use the SVD to find a low-rank approximation of the Ising coupling matrix while maintaining very high accuracy. This decomposition requires substantially fewer nonzeros to represent the dense Ising coupling matrix. Second, we develop a method to translate the low-rank decomposition to a hardware implementation that uses only sparse resistive interconnections. We validate DaS on the MU-MIMO detection problem, important in modern telecommunications. Our results indicate that as problem sizes scale, DaS can achieve dense Ising coupling using only 5%-20% of the resistors needed for brute-force dense connections (which would be physically infeasible in ICs). We also outline a crossbar-style physical layout scheme for realizing sparse resistive networks generated by DaS.

In this paper, we report new results on a novel Ising machine technology for solving combinatorial optimization problems using networks of coupled self-sustaining oscillators. Specifically, we present several working hardware prototypes using CMOS electronic oscillators, built on bread-boards/perfboards and PCBs, implementing Ising machines consisting of up to 240 spins with programmable couplings. We also report that, just by simulating the differential equations of such Ising machines of larger sizes, good solutions can be achieved easily on benchmark optimization problems, demonstrating the effectiveness of oscillator-based Ising machines.

A common complaint from users of device models is that the “better” the model, the longer it takes to simulate. Modelling based on interpolation between sampled data points is attractive in this context because it offers low model evaluation times. Although such “table-based” modelling has a long history, important conceptual and implementation issues have been obscure in the literature. These issues include: separating the algebraic (“DC”) and dynamic (“charge/flux”) components properly; extrapolation outside sampled regions; smoothness; accuracy vs. computation vs. memory tradeoffs; and suitability of the table-based model for various analyses (such as DC, AC, transient, RF, etc., analyses). In this paper, we clarify precisely what functions should be sampled for a table-based device model to work properly in any analysis. We re-visit interpolation, showing that well-implemented cubic splines provide excellent smoothness and arbitrarily great accuracy at low, almost-constant evaluation cost. However, memory requirements increase with accuracy. We present a novel extrapolation scheme using passivity concepts that aids convergence. Using Berkeley MAPP, we demonstrate speedups of 150× in core BSIM model evaluations (translating to overall simulation speedups of 6-18×) with relative errors of 0.001%. Our approach can convert any existing device model to a smooth/accurate table-based model with small, fixed evaluation cost. Unlike previous work, our code will be released as open source, serving as a platform for the community to evaluate and experiment with table-based models quickly and conveniently.

Modern high-speed links and I/O subsystems often employ sophisticated coding strategies to boost error resilience and achieve multi-Gb/s throughput. The end-to-end analysis of such systems, which involves accurate prediction of worst-case and stochastic eye diagrams, is a challenging problem. Existing techniques such as Peak Distortion Analysis (PDA) typically predict overly pessimistic eye diagrams because they do not take into account the coding strategies employed. Monte-Carlo methods, on the other hand, often predict overly optimistic eye diagrams, and they are also very time-consuming. As an alternative, we present BEE, an accurate and efficient computational technique that applies dynamic programming algorithms to predict realistic worst-case and stochastic eye diagrams in modern high-speed links and I/O subsystems - with neither excessive pessimism nor undue optimism. BEE is able to fully and correctly take into account many features underlying modern communications systems, including arbitrary high-level transmit-side coding schemes and strategies, as well as various low-level non-idealities introduced by the underlying channel(s), such as inter-symbol interference (ISI) and crosstalk, asymmetric rise/fall times, jitter, parameter variability, etc. Furthermore, BEE accurately captures the fact that different received bits typically have widely different eye diagrams when a channel is driven by correlated bitstreams generated by coding strategies. We demonstrate BEE on links involving (7,4)-Hamming and 8b/10b SERDES encoders, featuring channels that give rise to multiple reflections, dispersion, loss, and overshoot/undershoot. BEE successfully predicts actual worst case eye openings in all these real-world systems, which can be twice as large as the eye openings predicted by overly pessimistic methods like PDA. Also, BEE can be an order of magnitude faster (and much more reliable) than Monte-Carlo based eye estimation methods.

Recently, general-purpose computing schemes have been proposed that use phase relationships to represent Boolean logic levels and employ self-sustaining nonlinear oscillators as latches and registers. Such phase-based systems have superior noise immunity relative to traditional level-encoded logic, hence are of interest for next-generation computing using nanodevices. However, the design of such systems poses special challenges for existing tools. We present a suite of techniques and tools that provide designers with efficient simulation and convenient visualization facilities at all stages of phase logic system design. We demonstrate our tools through a case study of the design of a phase logic finite state machine (FSM). We build this FSM and validate our design tools and processes against measurements. Our plan is to release our tools to the community in open source form.

We describe the Berkeley Model and Algorithm Prototyping Platform (MAPP), designed to facilitate experimentation with numerical algorithms and models. MAPP is written entirely in MATLAB and is available as open source under the GNU GPL.

Self-sustaining nonlinear oscillators of practically any type can function as latches and registers if Boolean logic states are represented physically as the phase of oscillatory signals. Combinational operations on such phase-encoded logic signals can be implemented using arithmetic negation and addition followed by amplitude limiting. With these, general-purpose Boolean computation using a wide variety of natural and engineered oscillators becomes potentially possible. Such phase-encoded logic shows promise for energy-efficient computing. It also has inherent noise immunity advantages over level-based logic.

We present ABCD-NL, a technique that approximates non-linear analog circuits using purely Boolean models, to high accuracy. Given an analog/mixed-signal (AMS) system (e.g., a SPICE netlist), ABCD-NL produces a Boolean circuit representation (e.g., an And Inverter Graph, Finite State Machine, or Binary Decision Diagram) that captures the I/O behaviour of the given system, to near SPICE-level accuracy, without making any apriori simplifications. The Boolean models produced by ABCD-NL can be used for high-speed simulation and formal verification of AMS designs, by leveraging existing tools developed for Boolean/hybrid systems analysis (e.g., ABC [1]). We apply ABCD-NL to a number of SPICE-level AMS circuits, including data converters, charge pumps, comparators, non-linear signaling/communications sub-systems, etc. Also, we formally verify the throughput of an AMS signaling system - modelled in SPICE using 22nm BSIM4 transistors, Booleanized with high accuracy using ABCD-NL, and property-checked using ABC.

We present ABCD-L, a scalable technique for Analog/Mixed Signal (AMS) modelling/verification that captures the continuous dynamics of Linear Time-Invariant (LTI) systems, using purely Boolean approximations, to any desired level of accuracy. ABCD-L's models can be used in conjunction with existing techniques for Boolean synthesis/verification/fast logic simulation, or with hybrid systems frameworks, to represent LTI dynamics without incurring the penalty of adding continuous variables. Unlike existing state-enumeration approaches like DAE2FSM [1], ABCD-L scales practically linearly with system size. We apply ABCD-L to I/O links composed of RC/RLGC units, capturing important analog effects like inter-symbol interference, overshoot/undershoot, ringing, etc. -- all using purely Boolean models. We also present a continuous-time differential equalizer example, where ABCD-L accurately reproduces key design-relevant AMS metrics, including the eye diagram correction achieved by the circuit. Furthermore, for real-world LTI systems, we demonstrate that ABCD-L can be applied in conjunction with Model Order Reduction (MOR) techniques; we use this to produce accurate Boolean models of an industry-scale power grid network (with 25849 nodes) made available by IBM. We also demonstrate that Boolean simulation using ABCD-L's models offers considerable speed-up over standard circuit simulation using linear multi-step numerical methods.

Defects or traps in semiconductors and nano devices that randomly capture and emit charge carriers result in low-frequency noise, such as burst and 1/f noise, that are great concerns in the design of both analog and digital circuits. The capture and emission rates of these traps are functions of the time-varying voltages across the device, resulting in nonstationary noise characteristics. Modeling of low-frequency, nonstationary noise in circuit simulators is a longstanding open problem. It has been realized that the low frequency noise models in circuit simulators were the culprits that produced erroneous noise performance results for circuits under strongly time-varying bias conditions. In this paper, we first identify an almost perfect analogy between trap noise in nano devices and the so-called ion channel noise in biological nerve cells, and propose a new approach to modeling and analysis of low-frequency noise that is founded on this connection. We derive two fully nonstationary models for traps, a fine-grained Markov chain model based on recent previous work and a completely novel coarse-grained Langevin model based on similar models for ion channels in neurons. The nonstationary trap models we derive subsume and unify all of the work that has been done recently in the device modeling and circuit design literature on modeling nonstationary trap noise. We also describe joint noise analysis paradigms for a nonlinear circuit and a number of traps. We have implemented the proposed techniques in a Matlab®based circuit simulator, by expanding the industry standard compact MOSFET model PSP to include a nonstationary description of oxide traps. We present results obtained by this extended model and the proposed simulation techniques for the low frequency noise characterization of a common source amplifier and the phase jitter of a ring oscillator.

With aggressive technology scaling and heightened variability, circuits such as SRAMs and DRAMs have become vulnerable to random telegraph noise (RTN). The bias dependence (i.e., non-stationarity), bi-directional coupling, and high inter-device variability of RTN present significant challenges to understanding its circuit-level effects. In this paper, we present two computer-aided design (CAD) tools, SAMURAI and MUSTARD, for accurately estimating the impact of non-stationary RTN on SRAMs and DRAMs. While traditional (stationary) analysis is often overly pessimistic (e.g., it overestimates RTN-induced SRAM failure rates), the predictions made by SAMURAI and MUSTARD are more reliable by virtue of non-stationary analysis.

We abstract the I/O functionality of continuous-time dynamical systems (e.g., SPICE netlists with combinational and sequential logic) as Finite State Machines (FSMs). This enables efficient simulation of large designs implemented with less-than-perfect devices and components, and also opens the door to formal verification of transistor-level designs against higher-level specifications. In particular, our automatically generated FSMs faithfully capture the behaviour of latches, flip-flops, and circuits constructed from them. Among other technical advances, we generalize an existing (binary-only) FSM-learning approach to arbitrary I/O alphabets, which empowers it to learn high-fidelity abstractions of multi-level-discretized, multi-input/multi-output systems. Our approach, when applied to correctly functioning latches and flip-flops, is able to learn compact, multi-input FSM abstractions whose predictions closely match SPICE simulations. In addition, we have also applied our technique to produce multi-level-discretized FSM representations of digital systems that nevertheless exhibit "analogish" traits, such as an over-clocked, error-prone D-flip-flop. For such circuits, the automatically learned FSM abstraction includes additional states that characterise "failure modes" of the circuit for specific input sequences (these failure modes are also confirmed by SPICE simulations). Finally, we demonstrate that our technique is also applicable to larger and more complex multi-input, multi-output systems; for example, we are able to automatically derive an accurate FSM abstraction of a 280-transistor (BSIM4), 0-to-5 increment/decrement counter.

Transient waveform sensitivities are useful in optimization and also provide direct insight into system metrics such as delay. We present a novel method for finding parametric waveform sensitivities that improves upon current transient adjoint methods, which suffer from quadratic complexity, by applying barycentric Lagrange interpolation to reduce computation to near linear in the time-interval of interest. We apply our technique to find sensitivities of a "nonlinear" Elmore-delay like metric in digital logic and biochemical pathway examples. Our technique achieves order-of-magnitude speedups over traditional adjoint and direct sensitivity computation.

Sub-harmonic injection locking (SHIL) is an interesting phenomenon in nonlinear oscillators that is useful in RF applications, e.g., for frequency division. Existing techniques for analysis and design of SHIL are limited to a few specific circuit topologies. We present a general technique for analysing SHIL that applies uniformly to any kind of oscillator, is highly predictive, and offers novel insights into fundamental properties of SHIL that are useful for design. We demonstrate the power of the technique by applying it to ring and LC oscillators and predicting the presence or absence of SHIL, the number of distinct locks and their stability properties, lock range, etc.. We present comparisons with SPICE-level simulations to validate our method's predictions.

The design of a communications system is typically most effective only when each of its components can be accurately represented by a discrete, symbolic behavioural abstraction. Such abstractions, in addition to providing valuable design intuition, also enable highly efficient and scalable system-level simulation. However, given a SPICE-level description for a subsystem such as a latch, it is a challenge to come up with a discrete, symbol-level abstraction that accurately captures its continuous-time dynamics. Indeed, the manual construction of such an abstraction requires deep knowledge and understanding of the operation of the module in question; moreover, it is very time-consuming, tedious, error-prone and not easily scalable to larger designs. In recent work [1], we adapted methods from computational learning theory to develop an automated technique, DAE2FSM, that produces binary finite state machine (FSM) abstractions of non-linear analog/mixed-signal (AMS) circuits. In the present paper, we demonstrate the application of the DAE2FSM technique to automatically derive FSM abstractions for a mixed-signal communications circuit component, namely a current mode latch (CML) designed in IBM's 90nm LP process technology. We show that the FSMs learned by DAE2FSM not only capture the essence of the latch's behaviour during normal conditions, but also faithfully mimic its behaviour under adverse operating conditions (e.g., under lowered supply voltages). Moreover, in addition to a stand-alone CML, we also generate FSMs for cascades of two and three latches (such topologies are used in the design of power-efficient, bit-error optimised analog-to-digital converters). In spite of the inherent non-linearity of such systems, and in spite of the pronounced “analog-ness” of the waveforms in question, our FSM abstractions are able to produce discrete-time symbol sequences that closely match the data points obtained by sampling from continuous-time SPICE simulations.

Abstraction of circuits is desirable for faster simulation and high-level system verification. In this paper, we present an algorithm that derives a Mealy machine from differential equations of a circuit by learning input-output trajectories. The key idea is adapted from Angluin's DFA (deterministic finite automata) learning algorithm [1] that learns a DFA from another DFA. Several key components of Angluin's algorithm are modified so that it fits in our problem setting, and the modified algorithm also provides a reasonable partitioning of the continuous state space as a by-product. We validate our algorithm on a latch circuit and an integrator circuit, and demonstrate that the resulting FSMs inherit important behaviors of original circuits.

With aggressive technology scaling and heightened variability, SRAMs and DRAMs have become vulnerable to Random Telegraph Noise (RTN). The bias-dependent, random temporal nature of RTN presents significant challenges to understanding its effects on circuits. In this paper, we propose MUSTARD, a technique and tool for predicting the impact of RTN on SRAMs/DRAMs in the presence of variability. MUSTARD enables accurate, non-stationary, two-way-coupled, discrete stochastic RTN simulation seamlessly integrated with deterministic, continuous circuit simulation. Using MUSTARD, we are able to predict experimentally observed RTN-induced failures in SRAMs, and generate statistical characterisations of bit errors in SRAMs and DRAMs. We also present MUSTARD-generated results showing the effect of RTN on DRAM retention times.

In latest CMOS technologies, Random Telegraph Noise (RTN) has emerged as an important challenge for SRAM design. Due to rapidly shrinking device sizes and heightened variability, analytical approaches are no longer applicable for characterising the circuit-level impact of non-stationary RTN. Accordingly, this paper presents SAMURAI, a computational method for accurate, trap-level, non-stationary analysis of RTN in SRAMs. The core of SAMURAI is a technique called Markov Uniformisation, which extends stochastic simulation ideas from the biological community and applies them to generate realistic traces of non-stationary RTN in SRAM cells. To the best of our knowledge, SAMURAI is the first computational approach that employs detailed trap-level stochastic RTN generation models to obtain accurate traces of non-stationary RTN at the circuit level. We have also developed a methodology that integrates SAMURAI and SPICE to achieve a simulation-driven approach to RTN characterisation in SRAM cells under (a) arbitrary trap populations, and (b) arbitrarily time-varying bias conditions. Our implementation of this methodology demonstrates that SAMURAI is capable of accurately predicting non-stationary RTN effects such as write errors in SRAM cells.

We describe ModSpec, a MATLAB/Octave based specification format suitable for modelling devices across a wide variety of application domains, including circuits, optics, fluidics and biology. The ModSpec format and associated API are centered around describing the nonlinear differential equations at the core of any device model. The format is open, general and easy to use, and is supported by toolchains that translate and automatically differentiate models, set up equations for systems of interacting devices, and provide simulation facilities. We illustrate the use of ModSpec for modelling semiconductor, photovoltaic, fluidic and neuronal devices and systems.

We present a new manifold construction and parameterization algorithm for model reduction approaches based on projection on manifolds. The new algorithm employs two key ideas: (1) we define an ideal manifold for nonlinear model reduction to be the solution of a set of differential equations with the property that the tangent space at any point on the manifold spans the same subspace as the low-order subspace (e.g., Krylov subspace generated by moment-matching techniques) of the linearized system; (2) we propose the concept of normalized integral curve equations, which are repeatedly solved to identify an almost-ideal manifold. The manifold constructed by our algorithm inherits the important property in that it covers important system responses such as DC and AC responses. It also preserves better local distance metrics on the manifold, thanks to the employment of normalized integral curve equations. To gauge the quality of the resulting manifold, we also derive an error bound of the moments of linearized systems, assuming moment-matching techniques are employed to generate low-order subspaces for linearized systems. The algorithm is also more systematic and generalizable to higher dimensions than the ad hoc procedure in. We illustrate the key ideas through a simple 2-D example. We also combine this new manifold construction and parameterization algorithm with maniMOR to generate reduced models for a quadratic nonlinear system and a CMOS circuit. Simulation results are provided, together with comparisons to full models as well as TPWL reduced models.

Oscillations and rhythmic activity are seen in natural and man-made systems. Dynamics of oscillators can be compactly described by phase domain models. Phase equations for periodic, single-frequency oscillators have been developed and utilized in analyzing oscillation phenomena that arise in electronic systems, circadian clocks, and the nervous system. We consider quasi-periodic oscillators and present a general phase model theory and numerical techniques for the construction of phase equations for multi-frequency oscillators. We demonstrate the utility of these phase equations in analyzing oscillators experiencing perturbations.

We extend the concept of timing/phase macromodels, previously established rigorously only for oscillators, to apply to general systems, both non-oscillatory and oscillatory. We do so by first establishing a solid foundation for the timing/phase response of any nonlinear dynamical system, then deriving a timing/phase macromodel via nonlinear perturbation analysis. The macromodel that emerges is a scalar, nonlinear time-varying equation that accurately characterizes the system's phase/timing responses. We establish strong links of this technique with projection frameworks for model order reduction. We then present numerical methods to compute the phase model. The computation involves a full Floquet decomposition — we discuss numerical issues that arise if direct computation of the monodromy matrix is used for Floquet analysis, and propose an alternative method that are numerically superior. The new method has elegant connections to the Jacobian matrix in harmonic balance method (readily available in most RF simulators). We validate the technique on several highly nonlinear systems, including an inverter chain and a firing neuron. We demonstrate that the new scalar nonlinear phase model captures phase responses under various types of input perturbations, achieving accuracies considerably superior to those of reduced models obtained using LTI/LPTV MOR methods. Thus, we establish a powerful new way to extract timing models of combinatorial/sequential systems and memory (e.g., SRAMs/DRAMs), synchronization systems based on oscillator enslaving (e.g., PLLs, injection-locked oscillators, CDR systems, neural processing, energy grids), signal-processing blocks (e.g., ADCs/DACs, FIR/IIR filters), etc.

Injection locking analysis based on classical Adler's equation is limited to LC oscillators as it is dependent on quality factor. In this paper, we present the generalized Adler's equation applicable for injection locking analysis on oscillators independent of the circuit topology. The equation is obtained by averaging the PPV phase macromodel. The procedure is considerably simple and handy to determine the locking range for arbitrary shape small AC injection signal. Analytical equations for injection locking dynamics are formulated using the generalized Adler's equation and validated with the PPV simulations.

Failures and yield problems due to parameter variations have become a significant issue for sub-90-nm technologies. As a result, CAD algorithms and tools that provide designers the ability to estimate the effects of variability quickly and accurately are being urgently sought. The need for such tools is particularly acute for static RAM (SRAM) cells and integrated oscillators, for such circuits require expensive and high-accuracy simulation during design. We present a novel technique for fast computation of parametric yield. The technique is based on efficient, adaptive geometric calculation of probabilistic hypervolumes subtended by the boundary separating pass/fail regions in parameter space. A key feature of the method is that it is far more efficient than Monte-Carlo, while at the same time achieving better accuracy in typical applications. The method works equally well with parameters specified as corners, or with full statistical distributions; importantly, it scales well when many parameters are varied. We apply the method to an SRAM cell and a ring oscillator and provide extensive comparisons against full Monte-Carlo, demonstrating speedups of 100–1000×.

Summary form only given, as follows. Although analogue and mixed-signal design is greatly complicated by numerous design choices, the management of these design choices presents significant opportunities for optimising designs for desired tradeoffs in performance and high production yield. This tutorial describes analog design and EDA methods beginning with MOS transistors and concluding with PLLs as complete mixed-signal systems. Tutorial topics include: (1) tradeoffs and optimisation in analogue CMOS design through transistor drain current, inversion coefficient, and channel length selections; (2) transistor sizing rules, rules for transistor groups, and robust Pareto optimisation of circuits; (3) analogue synthesis, hierarchical design, and yield optimisation; and (4) behavioral modelling of oscillators and PLLs using nonlinear phase macro models that capture jitter and phase noise, injection locking, PLL lock and capture phenomena, and cycle slipping. Tutorial topics are interrelated with each other and illustrated using actual designs. Finally, future directions for analogue design and EDA are suggested, including applications to biological systems such as mammalian circadian rhythms. This tutorial is targeted to analogue and mixed-signal designers, EDA developers and users, design managers, and advanced university students.

Coupled oscillator networks occur in various domains such as biology, astrophysics and electronics. In this paper, we present a comprehensive procedure for rapid and accurate simulation of large coupled oscillator networks using widely accepted, fully-nonlinear perturbation projection vector (PPV) phase macromodels. We validate our method against full simulation of 20times20 coupled network of Brusselator biochemical oscillator and obtain computational speedups of 170x over full simulation. Furthermore, we apply the method to study self-organization phenomenon of Brusselator under asymmetric coupling and time period variations.

Previous model order reduction methods fit into the framework of identifying the low-order linear subspace and using the linear projection to project the full state space into the low-order subspace. Despite its simplicity, the macromodel might automatically include redundancies.

We present algorithms for automated macromodeling of nonlinear mixed-signal system blocks. A key feature of our methods is that they automate the generation of general-purpose macromodels that are suitable for a wide range of time- and frequency-domain analyses important in mixed-signal design flows. In our approach, a nonlinear circuit or system is approximated using piecewise-polynomial (PWP) representations. Each polynomial system is reduced to a smaller one via weakly nonlinear polynomial model-reduction methods. Our approach, dubbed PWP, generalizes recent trajectory-based piecewise-linear approaches and ties them with polynomial-based model-order reduction, which inherently captures stronger nonlinearities within each region. PWP-generated macromodels not only reproduce small-signal distortion and intermodulation properties well but also retain fidelity in large-signal transient analyses. The reduced models can be used as drop-in replacements for large subsystems to achieve fast system-level simulation using a variety of time- and frequency-domain analyses (such as dc, ac, transient, harmonic balance, etc.). For the polynomial reduction step within PWP, we also present a novel technique [dubbed multiple pseudoinput (MPI)] that combines concepts from proper orthogonal decomposition with Krylov-subspace projection. We illustrate the use of PWP and MPI with several examples (including op-amps and I/O buffers) and provide important implementation details. Our experiments indicate that it is easy to obtain speedups of about an order of magnitude with push-button nonlinear macromodel-generation algorithms.

Envelope-following methods face special challenges when applied to oscillators because of their fundamental property of dynamically changing frequencies. In this paper, we present a novel and robust approach for oscillator envelope following. Our method combines, unifies, and extends ideas from two prior oscillator envelope-following approaches, namely, Petzold's method and the warped multitime partial differential equation. Our technique uses two extra system unknowns, as well as two extra ldquophase conditionrdquo equations, to track quantities related to dynamical frequency/time-period changes. These advances confer significant robustness, without appreciable computational overhead. We validate our method on LC, ring, and crystal oscillators, accurately predicting frequency and amplitude modulations, as well as transient startup envelopes. Speedups of one to two orders of magnitude are obtained over traditional alternatives.

Characterizing setup/hold times of latches and registers, which is a task crucial for achieving timing closure of large digital designs, typically occupies months of computation in semiconductor industries. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation ; this nonlinear algebraic formulation is derived from, and embeds within it, the state-transition function of the latch. We first present a technique to characterize setup and hold times independently of each other: by decoupling into two equations and and solving each equation using the Newton-Raphson method. Next, we also present a method for interdependent characterization of latch setup/hold times - a core component of techniques for pessimism reduction in timing analysis. We achieve this by solving the underdetermined nonlinear equation using a Moore-Penrose pseudoinverse-based Newton method. Furthermore, we use null-space information from the Newton's Jacobian matrix to efficiently find constant-clock-to- contours (in the setup/hold time plane) via an Euler-Newton curve-tracing procedure. We validate fast convergence and computational advantage for independent characterization on transmission gate and latch/register structures, obtaining speedups of , at high levels of accuracy, over the current standard of binary search. We validate the method for interdependent characterization on true single-phased clock and , obtaining speedups of more than 10 for tracing 17-24 points, over prior approaches while achieving superior accuracy; this speedup linearly increases with the precision with which curve tracing is desired. We also apply our method for interdependent characterization on a transmission gate register to illustrate limitations of our method.

We present a fundamentally new approach, ADME, for extracting highly accurate delay models of a wide variety of digital gates. The technique is based on trajectory-piecewise automated nonlinear macromodelling methods adapted from the mixed-signal/RF domain. Advantages over prior current-source models include rapid automated extraction from SPICE-level netlists, transparent retargetability to different design styles and technologies, and the ability to correctly and holistically account for complex input waveform shapes, nonlinear and linear loading, multiple input switching, effects of internal state, multiple I/Os, supply droop and substrate interference. We validate ADME on a variety of digital gates, including multi-input NAND, NOR, XOR gates, a full adder, a multilevel cascade of gates and a sequential latch. Our results confirm excellent model accuracy at the detailed waveform level and testify to the promise of ADME for sustainable gate delay modelling at nanoscale technologies.

We present a robust, automated oscillator macromodeling technique for extracting comprehensive phase and amplitude macromodels from oscillators' SPICE circuit descriptions. The macromodels are able to correctly predict oscillator response in the presence of interference at far lower computational cost than that of full SPICE-level simulation, while retaining the simulation accuracy. We find many applications for the proposed macromodeling technique, which include injection locking prediction, fast simulation of coupled oscillating systems, and fast PLL transient simulation and jitter analysis. We demonstrate the applications on some oscillator-based systems, and compare results against full SPICE-level simulation. Experimental results show that the macromodels capture the behavior of the oscillator systems accurately, and provide speedups of over three orders of magnitude.

Photonic interconnects have the long-term potential to reduce latency and crosstalk while increasing signalling bandwidth. This tutorial-style presentation for non-experts will provide a simple overview of photonics as it relates to the interconnect problem. We will touch upon the challenges faced by on-chip and chip-to-chip communications that motivate micro-photonic (optical) interconnects, and provide an introduction to the basics of optics. Topics such as the system impact of optical interconnects, impact on cache, chip-to-chip communication and global clock distribution will be examined. Practical feasibility issues and limitations related to power, speed, and technology hurdles will be evaluated. The talk will conclude with a look at some fascinating recent developments that bode well for the future of micro-photonic interconnects.

Interdependent characterization of latch setup/hold times is a core component of techniques for pessimism reduction via Setup/Hold Interdependence Aware Static Timing Analysis (SHIA-STA) [1], [2]. We present an efficient and novel method for such characterization, by formulating the interdependent setup-hold time problem as an underdetermined nonlinear equation h(τs, τh) = 0, which we derive from the latch's state-transition function. We solve this equation numerically using a Moore-Penrose Newton method. Further, we use null-space information from the Newton's Jacobian matrix to efficiently find constant-clock-to-Q contours (in the setup/hold time plane), via an Euler-Newton curve tracing procedure. We validate the method on TSPC and C2MOS registers, obtaining speedups of more than 20 x over prior approaches while achieving superior accuracy. This speedup increases linearly with the precision with which curve tracing is desired. In view of the importance and large computational expense of latch characterization in industry today, the new technique represents a significant enabling technology for dramatically speeding up industrial timing closure flows.

The PPV is a robust phase domain macromodel for oscillators. It has been proven to predict oscillators' responses correctly under small signal perturbations, and capture nonlinear phase effects such as injection locking/pulling. In this work, we present a novel approach to extend the PPV macromodel to handle variability in circuit parameters. We derive a modified PPV-based phase equation in which parameter variations are modelled as special inputs. An important feature of our technique is that it avoids PPV re-extraction, this resulting in great convenience and efficiency in its use for, e.g., Monte Carlo type simulations. Using LC and ring oscillators as examples, we demonstrate the capability of the proposed technique for capturing parameter variation effects in injection locking analysis. Simulation results show that our new approach accurately predicts the maximum locking range of oscillators with speedups of two orders of magnitude over direct simulation.

Characterizing setup/hold times of latches and registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(tau) = 0 derived using state-transition functions, and then solving this equation by Newton-Raphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for accurate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C2MOS latch/register structures, obtaining speedups of 4-10times over the current standard of binary search

The paper describes the recent state of the art in hierarchical analog synthesis, with a strong emphasis on associated techniques for computer-aided model generation and optimization. Over the past decade, analog design automation has progressed to the point where there are industrially useful and commercially available tools at the cell level-tools for analog components with 10-100 devices. Automated techniques for device sizing, for layout, and for basic statistical centering have been successfully deployed. However, successful component-level tools do not scale trivially to system-level applications. While a typical analog circuit may require only 100 devices, a typical system such as a phase-locked loop, data converter, or RF front-end might assemble a few hundred such circuits, and comprise 10 000 devices or more. And unlike purely digital systems, mixed-signal designs typically need to optimize dozens of competing continuous-valued performance specifications, which depend on the circuit designer's abilities to successfully exploit a range of nonlinear behaviors across levels of abstraction from devices to circuits to systems. For purposes of synthesis or verification, these designs are not tractable when considered "flat." These designs must be approached with hierarchical tools that deal with the system's intrinsic design hierarchy. This paper surveys recent advances in analog design tools that specifically deal with the hierarchical nature of practical analog and RF systems. We begin with a detailed survey of algorithmic techniques for automatically extracting a suitable nonlinear macromodel from a device-level circuit. Such techniques are critical to both verification and synthesis activities for complex systems. We then survey recent ideas in hierarchical synthesis for analog systems and focus in particular on numerical techniques for handling the large number of degrees of freedom in these designs and for exploring the space of performance tradeoffs early in the design process. Finally, we briefly touch on recent ideas for accommodating models of statistical manufacturing variations in these tools and flows

Standard small-signal analysis methods for circuits break down for oscillators because small-input perturbations result in arbitrarily large-output changes, thus invalidating fundamental assumptions for small-signal analysis. In this paper, we propose a novel oscillator ac approach remedying this situation, thus restoring validity and rigour to small-signal analysis of oscillators. Our approach centers around a novel general equation formulation for circuits that we term the Generalized Multitime Partial Differential Equations (GeMPDE). While this formulation is broadly applicable to any kind of circuit or dynamical system, we show that it has unique advantages for oscillators in that small-input perturbations now lead to small output ones, thus making small-signal analysis valid. A key feature of our approach is to solve for bivariate-frequency variables with the help of novel augmenting-phase-condition equations. Unlike prior oscillator-analysis methods, which require special handling of the phase mode, our GeMPDE-based small-signal analysis provides both amplitude and frequency characteristics in a unified manner and is applicable to any kind of oscillator described by differential equations. We obtain speedups of 1-2 orders of magnitude over the transient-simulation approach commonly used today by designers for oscillator-perturbation analysis

We present a novel methodology suitable for fast, correct design of modern PLLs. The central feature of the methodology is its use of accurate, nonlinear behavioral models for the VCO within the PLL, thus removing the need for many time-consuming SPICE-level simulations during the design process. We apply the new methodology to design a novel injection-aided PLL that acquires lock 3/spl times/ faster than prior designs, without trading off other design metrics such as jitter. We demonstrate how existing design methodologies based on behavioral simulation are incapable of leading to our new PLL design. The nonlinear behavioral simulations employed in our methodology are about 2 orders of magnitude faster than transistor-level ones, resulting in an overall design productivity gain of an order of magnitude.

We address the problem of fast and accurate computational analysis of large networks of coupled oscillators arising in nanotechnological and biochemical systems. Such systems are computationally and analytically challenging because of their very large sizes and the complex nonlinear dynamics they exhibit. We develop and apply a nonlinear oscillator macromodel that generalizes the well-known Kuramoto model for interacting oscillators, and demonstrate that using our macromodel provides important qualitative and quantitive advantages, especially for predicting self-organization phenomena such as spontaneous pattern formation. Our approach extends and applies recently-developed computational methods for macromodel ling electrical oscillators, and features both phase and amplitude components that are extracted automatically (using numerical algorithms) from more complex differential-equation oscillator models available in the literature. We apply our approach to networks of tunneling phase logic (TPL) and Brusselator biochemical oscillators, predicting a variety of spontaneous pattern generation phenomena. Comparing our results with published measurements of spiral, circular and other pattern formation, we show that we can predict these phenomena correctly, and also demonstrate that prior models (like Kuramoto's) cannot do so. Our approach is more than 3 orders of magnitude faster than techniques that are comparable in accuracy.

We present an efficient method for automatically extracting unified amplitude/phase macromodels of arbitrary oscillators from their SPICE-level circuit descriptions. Such comprehensive oscillator macromodels are necessary for accuracy when speeding up simulation of higher-level circuits/systems, such as PLLs, in which oscillators are embedded. Standard MOR techniques for linear time invariant (LTI) and varying (LTV) systems are not applicable to oscillators on account of their fundamentally nonlinear phase behavior. By employing a cancellation technique to deflate out the phase component, we restore the validity and efficacy of Krylov-subspace-based LTV MOR techniques for macromodelling oscillator amplitude responses. The nonlinear phase response is re-incorporated into the macromodel after the amplitude components have been reduced. The resulting unified macromodels predict oscillator waveforms, in the presence of any kind of input or interference, at far lower computational cost than full SPICE-level simulation, and with far greater accuracy compared to existing macromodels. We demonstrate the proposed techniques on LC and ring oscillators, obtaining speedups of 30-120/spl times/ with no appreciable loss of accuracy, even for small circuits.

PPV phase macromodels are important for speeding up simulation of oscillator related circuits, such as PLLs, without sacrificing accuracy. Prior numerical methods for extracting PPVs face very significant robustness and accuracy problems when confronted with digitally controlled oscillators (DCOs, core building blocks in digital phase-locked loops), due to large RC time-constants from gated capacitors. In this paper, we present a hierarchical harmonic balance based technique for numerically extracting the PPV of DCOs from their SPICE-level circuit descriptions. The proposed method applies hierarchical circuit partitioning and multi-level Newton methods to achieve dramatically superior convergence and PPV accuracy in the presence of large RC time-constants. We validate the method on a large DCO with many gated capacitors and demonstrate that it can extract the PPV efficiently and robustly, succeeding when prior methods fail. The method also provides speedups of an order of magnitude for large circuits, in addition to having significantly smaller memory requirements.

In this paper, we propose a novel envelope-following method which is uniformly applicable to both non-autonomous and oscillatory circuits. A key feature of our technique is the use of an efficient minimum least squares solution technique to solve an underdetermined envelope system directly. This leads to a general purpose approach which is much easier to solve than previous phase condition based envelope-following method, improving numerically robustness dramatically. We validate our method on a variety of autonomous and non-autonomous circuits, including a PLL in transition to lock. The new method provides speedups of 1-2 orders of magnitude over transient simulation, while obtaining results that are equally or more accurate.

We present a generalization of standard AC analysis to oscillators by exploiting least-squares solution techniques. This provides an attractive alternative to the current practice of employing transient simulation for small signal analysis of oscillators. Unlike phase condition based oscillator analysis techniques, which suffer from numerical artifacts, the least-squares approach of this paper results in a robust and efficient oscillator AC technique. We validate our method on LC and ring oscillators, obtaining speedups of 1-3 orders of magnitude over transient simulation, and 4-6×over phase-condition-based techniques.

We present a novel method for generating small, accurate PLL macromodels that capture transient response and jitter performance with unprecedented accuracy, while offering large speedups. The method extracts and uses a highly accurate oscillator phase macromodel termed the TP-PPV macromodel. The core idea behind the novel extraction procedure is to combine concepts from strongly nonlinear trajectory piecewise macromodeling techniques together with PPV-based timeshifted nonlinear phase macromodels. As a result, TP-PPV generated macromodels offer excellent global as well as local fidelity. These properties are necessary for handing large excursions in PLL control voltages during capture/lock in, e.g., hopping frequency synthesizers. We validate TP-PPV on a 5-stage interpolative ring VCO based PLL and compare results against full simulation, as well as against prior macromodels. We show that, unlike prior macromodels that only work well when the control voltage of the VCO has small excursions, the TP-PPV macromodel provides near-perfect matches against full SPICElevel simulation over a wide range of design scenarios, while achieving speedups of about three orders of magnitude.

A unique feature of oscillators is that small but sustained external perturbations lead to unboundedly large changes in phase, thereby making standard harmonic balance (HB) inapplicable to realistic oscillator phase macromodels. In this paper, we rectify this situation by presenting a novel extension of HB that is capable of handling oscillator phase macro-models. Key to the new method, termed PPV-HB, is a formulation that separates unboundedly increasing phase terms from the bounded, periodic components. PPV-HB can be used not only on individual oscillators, but it also enables the application of HB-like techniques for simulating system-level equation systems composed of higher-level macromodels of blocks. We validate PPV-HB on individual oscillators and a PLL system, demonstrating excellent matches with transient simulation using phase macromodels. Speedups of 1-2 orders of magnitude are obtained, over and above additional speedups of another 2-3 orders of magnitude that stem from using macromodels (as opposed to full circuit simulation)

Homotopy/continuation methods are attractive for finding dc operating points of circuits because they offer theoretical guarantees of global convergence. Existing homotopy approaches for circuits are, however, often ineffective for large mixed-signal applications. In this paper, we describe a robust homotopy technique that is effective for solving large metal-oxide-semiconductor (MOS)-based mixed-signal circuits. We demonstrate how certain common circuit structures involving turning-point nesting can lead to extreme inefficiency, or failure, of conventional probability-one homotopy methods. We also find that such situations can lead to numerical ill-conditioning and homotopy paths that fold back upon themselves, leading to algorithm failure. Our new homotopy model for MOS devices, dubbed Arc-tangent Schichman-Hodges (ATANSH), features decoupled continuation parameters that are instrumental in avoiding these problems. ATANSH-based homotopy methods in production use have led to the routine solution of large previously hard-to-solve industrial circuits, several examples of which are presented.

Phase-locked loops (PLLs) are widely used in electronic systems. As PLL malfunction is one of the most important factors in re-fabs of SoCs, fast simulation of PLLs to capture non-ideal behavior accurately is an immediate, pressing need in the semiconductor design industry. In this paper, we present a nonlinear macromodel based PLL simulation technique that is considerably more accurate than prior linear PLL simulation techniques. Our method is able to accurately capture transient behavior and faithfully estimate timing jitter in noisy PLLs. We demonstrate the proposed technique on ring and LC voltage-controlled oscillator (VCO) based PLLs, and compare results against linear PLL macromodels and full SPICE-level simulation. We show that, unlike prior linear macromodel based approaches, the proposed nonlinear technique captures the dynamics of complex phenomena such as locking, cycle slipping and power supply noise induced PLL jitter, replicating qualitative features from full SPICE simulations accurately while providing speedups of over two orders of magnitude.

We present applications of a recently developed automated nonlinear macromodelling approach to the important problem of macromodelling high-speed output buffers/drivers. Good nonlinear macromodels of such drivers are essential for fast signal-integrity and timing analysis in high-speed digital design. Unlike traditional black-box modelling techniques, our approach extracts nonlinear macromodels of digital drivers automatically from SPICE-level descriptions. Thus it can naturally capture transistor-level nonlinearities in the macromodels, resulting in far more accurate signal integrity analysis, while retaining significant speedups. We demonstrate the technique by automatically extracting macromodels for two typical digital drivers. Using the macromodel, we obtain about 8x speedup in average with excellent accuracy in capturing different loading effects, crosstalk, simultaneous switching noise (SSN), etc.

Linear periodically time-varying (LPTV) abstractions are useful for a variety of communication and computer subsystems. In this paper, we present a novel operator-based model-order reduction (MOR) algorithm for reducing large LPTV systems to smaller ones, a capability useful for system-level performance analysis. Our pro-cedure is based on generalizing existing matrix-based Krylov-sub-space algorithms to arbitrary function-space operators. Practical benefits of our approach include significantly enhanced algorithm and code modularity, compared to previous LPTV-MOR approaches based on a-priori discretization. We demonstrate the use of the pro-posed technique on several circuit examples.

We present a novel method for finding periodic steady states of general classes of oscillators robustly. The new method, which we term the multi-harmonic probe (MHP) technique, generalizes the well-known technique of augmenting harmonic balance (HB) for oscillators using an external probe. By using non-sinusoidal periodic probes, MHP enhances the applicability of the standard probe method (which uses purely sinusoidal probes) to broader classes of oscillators. We thus obtain a general and robust method for the periodic steady state of any kind of oscillator. Results on LC and ring oscillator circuits are presented that testify to the efficacy of our approach.

Envelope-following methods face special challenges when applied to oscillators because of their fundamental property of dynamically-changing frequencies. In this paper, we present a novel and robust approach for oscillator envelope following. Our method combines, unifies and extends ideas from two prior oscillator envelope-following approaches, Petzold's method and the WaMPDE. Our technique uses two extra system unknowns, as well as two extra "phase condition" equations, to track quantities related to dynamical frequency/time-period changes. These advances confer significant robustness without appreciable computational overhead. We validate our method on LC, ring and crystal oscillators, predicting frequency and amplitude modulations as well as transient startup envelopes accurately. Speedups of 1-2 orders of magnitude are obtained over traditional alternatives.

Standard small-signal analysis methods for circuits break down for oscillators because small input perturbations result in arbitrarily large output changes, thus invalidating fundamental assumptions for small-signal analysis. In this paper, we propose a novel oscillator-AC (OAC) approach remedying this situation, thus restoring validity and rigour to small-signal analysis of oscillators. Our approach centers around a novel, general equation formulation for circuits that we term the GeMPDE. A key feature of our approach is to solve for bivariate frequency variables with the help of novel augmenting phase condition equations. Our GeMPDE-based small-signal analysis provides both amplitude and frequency characteristics in a unified manner and is applicable to any kind of oscillator described by differential equations. We obtain speedups of 1-2 orders of magnitude over the transient simulation approach commonly used today by designers for oscillator perturbation analysis. We also demonstrate and explain how our linearization approach captures the inherently nonlinear phenomenon of injection locking in oscillators.

We explore the stability properties of time-domain numerical methods for multitime partial differential equations (MPDEs) in detail. We demonstrate that simple techniques for numerical discretization can lead easily to instability. By investigating the underlying eigenstructure of several discretization techniques along different artificial time scales, we show that not all combinations of techniques are stable. We identify choices of discretization method and step size, along fast and slow time scales, that lead to robust, stable time-domain integration methods for the MPDE. One of our results is that applying overstable methods along one time-scale can compensate for unstable discretization along others. Our novel integration schemes bring robustness to time-domain MPDE solution methods, as we demonstrate with examples.

Estimating interference from large digital blocks, and its effect on on-chip power-distribution networks, is extremely important in deep submicron digital and mixed-signal IC design, especially for systems-on-a-chip. In this paper, we present automated extraction techniques that can be used to generate families of small, time-varying macromodels of digital cell libraries from SPICE-level descriptions. Our automated digital aggressor macromodeling for interference noise (ADAMIN) approach is based on importing and adapting the time-varying Pade/spl acute/ method, for linear time-varying model reduction, from the mixed-signal macromodeling domain. Our approach features naturally higher accuracy than previous ones and, in addition, offers the user a tradeoff between accuracy and macromodel complexity. Extracted macromodels capture a variety of noise interference mechanisms, including IR and L(dI/dT) drops for power rails. Using ADAMIN as a core, it is expected that library-characterization methodologies will evolve to include extracted, accurate-by-construction interference noise macromodels for digital cell blocks. Experimental results indicate speedups of several orders of magnitude over full SPICE-level circuits, with prediction accuracies considerably superior to those from commonly-used current-source-based aggressor models.

In this paper, we explore in detail the stability properties of time-domain numerical methods for multi-time partial differential equations (MPDEs). We demonstrate that simple techniques for numerical discretization can lead easily to instability. By investigating the underlying eigenstructure of several discretization techniques along different artificial time scales, we show that not all combinations of techniques are stable. We identify choices of discretization method and of step size along slow time scales that lead to robust, stable time-domain integration methods for the MPDE. One of our results is that applying overstable methods along one time-scale can compensate for unstable discretization along others. Our novel integration schemes bring robustness to time-domain MPDE solution methods, as we demonstrate with examples.

Noise analysis and power distribution network reliability assessment is extremely important in deep sub-micron digital and mixed-signal circuit design. Both relate closely to the nonlinear loading impact of digital circuits. Consequently, accurate estimation of the latter is critical. In this paper, we present extraction techniques that automatically generate a family of small, time-varying macromodels for digital cell libraries, at the time of their library characterization. Our approach is based on importing and adapting the time-varying pade (TVP) method, for linear time-varying (LTV) model reduction, from the mixed-signal macromodelling domain. Our approach features naturally higher accuracy than previous ones, and in addition, offers the user a tradeoff between accuracy and macromodel complexity. A key attraction of our approach is that it can be merged into cell library extraction methodologies to produce accurate-by-construction noise models for digital blocks. Simulations and comparisons confirming the efficacy of our approach are provided.

We present a method for extracting comprehensive amplitude and phase macromodels of oscillators from their circuit descriptions. The macromodels are based on combining a scalar, nonlinear phase equation with a small linear time-varying system to capture slowly-dying amplitude variations. The comprehensive macromodels are able to correctly predict oscillator response in the presence of interference at far lower computational cost than that of full SPICE-level simulation. We also present an efficient numerical method for capturing injection locking in oscillators, thereby improving on the classic technique of Adler (1946) in terms of accuracy and applicability to any kind of oscillator. We demonstrate the proposed techniques on LC and ring oscillators, comparing results from the macromodels against full SPICE-like simulation. Numerical experiments demonstrate speed tips of orders of magnitude, while retaining excellent accuracy.

We present a novel, general approach towards model-order reduction (MOR) of nonlinear systems that combines good global and local approximation properties. The nonlinear system is first approximated as piecewise polynomials over a number of regions, following which each region is reduced via polynomial model-reduction methods. Our approach, dubbed PWP, generalizes recent piecewise linear approaches and ties them with polynomial-based MOR, thereby combining their advantages. In particular, reduced models obtained by our approach reproduce small-signal distortion and intermodulation properties well, while at the same time retaining fidelity in large-swing and large-signal analyses, e.g., transient simulations. Thus our reduced models can be used as drop-in replacements for time-domain as well as frequency-domain simulations, with small or large excitations. By exploiting sparsity in system polynomial coefficients, we are able to make the polynomial reduction procedure linear in the size of the original system. We provide implementation details and illustrate PWP with an example.

The main effort in oscillator phase noise calculation and macromodeling lies in computing a vector function called the perturbation projection vector (PPV). Current techniques for PPV calculation use time-domain numerics to generate the system's monodromy matrix, followed by full or partial eigenanalysis. We present superior methods that find the PPV using only a single linear solution of the oscillator's time- or frequency-domain steady-state Jacobian matrix. The new methods are better suited for implementation in existing tools with harmonic balance or shooting capabilities (especially those incorporating "fast" variants), and can also be more accurate than explicit eigenanalysis. A key advantage is that they dispense with the need to select the correct one eigenfunction from amongst a potentially large set of choices, an issue that explicit eigencalculation-based methods have to face. We illustrate the new methods in detail using LC and ring oscillators.

Verifying circuits with two or more closely-spaced driving frequencies is important in RF and wireless communications, e.g., in the design of down-conversion mixers. Existing steady-state calculation methods, like harmonic balance, rely on Fourier series expansions to find the difference-frequency components typically of interest. Time-domain methods are, however, better suited for circuits with strong nonlinearities such as switching. Towards this end, we present a purely time-domain method for direct computation of difference tones in closely-spaced multi-tone problems. Our approach is based on multiple artificial time scales for decoupling the tones driving the circuit. Our method relies on a novel multi-time reformulation that expresses circuit equations directly in terms of time-scales corresponding to difference tones. We apply the new technique to an RF-CMOS mixer to predict baseband bit-streams and down-conversion gain and distortion, in two orders of magnitude less CPU time than traditional time-stepping simulation.

Fourier-envelope algorithms are an important component of the mixed-signal/RF verification toolbox. In this paper, we address the unpredictability and lack of robustness that has been reported for these algorithms. We show that the problem stems from fast oscillations in envelopes that are expected to be slowly varying. We demonstrate that this is related to the fact that the envelope equations are always stiff, whether or not the underlying system is. We show that careful choice of envelope initial conditions is necessary to obtain useful solutions, and propose two techniques for finding good initial conditions. Applying these, and solving the envelope equations with stiffly-stable numerical methods, we improve the robustness and reliability of Fourier-envelope methods. We illustrate the new methods with a direct-downconversion mixer circuit.

Wireless transceivers for digital telecommunications are heterogeneous systems that combine digital hardware, software and analog circuitry. The pressure to miniaturization and lower power consumption for these transceivers imposes tight specifications on their analog RF parts. Many aspects of RF circuits cannot be simulated accurately and efficiently with a classical circuit-level SPICE approach. In this paper three important simulation problems for RF circuits are addressed: 1. High-level simulation of analog and RF blocks for the determination of the specifications of the circuits. 2. Accurate circuit-level simulation of nonlinear circuits with time constants that differ largely. 3. Efficient and accurate computation of phase noise in RF oscillators. For each of these problems, solutions are proposed. These solutions illustrate that accurate and efficient simulations of RF communication circuits need a heterogeneous variety of advanced algorithms.

The main effort in oscillator phase noise calculation lies in computing a vector function called the Perturbation Projection Vector (PPV). Current techniques for PAVE calculation use time domain numerics to generate the system's monodromy matrix, followed by full or partial eigenanalysis. We present a superior method that finds the PPV using only a single linear solution of the oscillator's time- or frequency-domain steady-state Jacobian matrix. The new method is better suited for existing tools with fast harmonic balance or shooting capabilities, and also more accurate than explicit eigenanalysis. A key advantage is that it dispenses with the need to select the correct one-eigenfunction from amongst a potentially large set of choices, an issue that explicit eigencalculation based methods have to face.

We present a novel formulation, called the WaMPDE, for solving systems with forced autonomous components. An important feature of the WaMPDE is its ability to capture frequency modulation (FM) in a natural and compact manner. This is made possible by a key new concept: that of warped time, related to normal time through separate time scales. Using warped time, we obtain a completely general formulation that captures complex dynamics in autonomous nonlinear systems of arbitrary size or complexity. We present computationally efficient numerical methods for solving large practical problems using the WaMPDE. Our approach explicitly calculates a time-varying local frequency that matches intuitive expectations. Applications to voltage-controlled oscillators demonstrate speedups of two orders of magnitude.

We present a theory for reduced-order modelling of linear time-varying systems, together with efficient numerical methods for application to large systems. The technique, called TVP (Time-Varying Pade), is applicable to deterministic as well as noise analysis of many types of communication subsystems, such as mixers and switched-capacitor filters, for which existing model reduction techniques cannot be used. TVP is therefore suitable for hierarchical verification of entire communication systems. We present practical applications in which TVP generates macromodels which are more than two orders of magnitude smaller, but still replicate the input-output behaviour of the original systems accurately. The size reduction results in a speedup of more than 500.

We present a novel formulation, called the WaMPDE, for solving systems with forced autonomous components.An important feature of the WaMPDE is its ability to capture frequency modulation (FM) in a natural and compact manner.This is made possible by a key new concept: that of warped time, related to normal time through separate time scales.Using warped time, we obtain a completely general formulation that captures complex dynamics in autonomous nonlinear systems of arbitrary size or complexity.We present computationally efficient numerical methods for solving large practical problems using the WaMPDE.Our approach explicitly calculates a time-varying local frequency that matches intuitive expectations.Applied to VCOs, WaMPDE-based simulation results in speedups of two orders of magnitude over transient simulation.

Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact, nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterisation of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on practical electrical oscillators, and obtain good matches with measurements even at frequencies close to the carrier, where previous techniques break down.

We describe powerful new techniques for the analysis of RF circuits. Next-generation CAD tools based on such techniques should enable RF designers to obtain a more accurate picture of how their circuits will operate. These new simulation capabilities will be essential in order to reduce the number of design iterations needed to produce complex RF ICs. 1 Introduction Design methodology and superior computer-aided design tools are key to success in the integrated circuit (IC) business. They are particularly important in the case of radio-frequency (RF) IC applications, where the digital IC divide-and-conquerdesign style, based on partitioning by functional blocks and abstraction levels, does not apply. The goal of an RF designer is to get a manufacturable design that meets the specifications with minimum cost, under severe time-to-market constraints. Unlike traditional discretecomponent RF design, prototyping is practically impossible, and the validation of a design can only be done b...

We present a theory for reduced-order modelling of linear time-varying sys-tems, together with efficient numerical methods for application to large systems. The technique, called TVP (Time-Varying Padé), is applicable to deterministic as well as noise analysis of many types of communication subsystems, such as mixers and switched-capacitor filters, for which existing model reduction tech-niques cannot be used. TVP is therefore suitable for hierarchical verification of entire communication systems. We present practical applications in which TVP generates macromodels which are more than two orders of magnitude smaller, but still replicate the input-output behaviour of the original systems accurately. The size reduction results in a speedup of more than 500. 1

Article Estimating noise in RF systems Share on Authors: Jaijeet Roychowdhury Bell Laboratories, Murray Hall, New Jersey Bell Laboratories, Murray Hall, New JerseyView Profile , Alper Demir Bell Laboratories, Murray Hall, New Jersey Bell Laboratories, Murray Hall, New JerseyView Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 199–202https://doi.org/10.1145/288548.288612Online:01 November 1998Publication History 3citation252DownloadsMetricsTotal Citations3Total Downloads252Last 12 Months2Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

A new technique is presented for computing noise in nonlinear circuits. The method is based on a formulation that uses harmonic power spectral densities (HPSDs), using which a block-structured matrix relation between the second-order statistics of noise within a circuit is derived. The HPSD formulation is used to devise a harmonic-balance-based noise algorithm that requires O(nN log N) time and O(nN) memory, where n represents circuit size and N the number of harmonics of the large-signal steady state. The method treats device noise sources with arbitrarily shaped PSDs (including thermal, shot and flicker noises) handles noise input correlations and computes correlations between different outputs. The HPSD formulation is also used to establish the non-intuitive result that bandpass filtering of cyclostationary noise can result in stationary noise. The new technique is illustrated using an example that exhibits noise folding and interaction between harmonic PSD components. The results are validated against Monte-Carlo simulations. The noise performance of a large industrial integrated RF circuit (with >300 nodes) is also analyzed in less than 2 hours using the new method.

Widely-separated time scales appear in many electronic circuits, making traditional analysis difficult or impossible if the circuits are highly nonlinear. In this paper, an analyticalformulation and numerical methods are presented for treating strongly nonlinear multi-rate circuits effectively. Multivariate functions in the time domain are used to capturewidely separated rates efficiently, and a special partial differential equation (the MPDE) is shown to relate the multivariate forms of a circuit's signals. Time-domain and mixedfrequency-time simulation algorithms are presented for solving the MPDE. The new methods can analyze circuits that are both large and strongly nonlinear. Compared to traditional techniques, speedups of more than two orders of magnitude, as well as improved accuracy, are obtained.

A new technique for obtaining a DC operating point of large, hard-to-solve MOS circuits is reported in this paper. Based on homotopy, the technique relies on the provable global convergence of arc length continuation and uses a novel method for embedding the continuation parameter into MOS devices. The new embedding circumvents inefficiencies and numerical failures that limit the practical applicability of previous simpler embeddings. Use of the technique in a production environment has led to the routine solution of large, previously hard-to-solve circuits.

We describe an efficient algorithm for time-domain simulation of elements described by causal impulse responses. The computational bottleneck in the simulation of such elements is the need to compute convolutions at each time point. Hence, direct approaches for the simulation of such elements require time O(N/sup 2/), where N is the length of the simulation. We apply ideas from approximation theory to reduce this complexity to O(N log N) while maintaining double-precision accuracy. The only restriction imposed by our method is that the impulse response h(t) gets "smoother" as t goes to infinity. Essentially all physically reasonable impulse responses have this characteristic. The ideas presented can also be applied to time-domain simulation of elements described in the frequency domain, including those characterized by measured data. In this paper, we demonstrate the efficiency of the algorithm by applying it to the simulation of lossy transmission lines.

In this paper, a new linear-time technique is described for the simulation of lossy lines with frequency-independent R, L, C and G. Exact analytic forms are shown to exist for the frequency-independent lossy line, with application in both the new technique and the conventional convolution method. Numerical convolution formulae that exploit the analytic forms are presented. Experimental results for industrial circuits indicate that the new technique can be 10 and 50 times faster than the convolution and lumped-RLC methods, respectively, for long simulations.>

Article Free Access Share on Efficient transient simulation of lossy interconnect Authors: Jaijeet S. Roychowdhury Department of Electrical Engineering and Computer Sciences, University of California, Berkeley Department of Electrical Engineering and Computer Sciences, University of California, BerkeleyView Profile , Donald O. Pederson Department of Electrical Engineering and Computer Sciences, University of California, Berkeley Department of Electrical Engineering and Computer Sciences, University of California, BerkeleyView Profile Authors Info & Claims DAC '91: Proceedings of the 28th ACM/IEEE Design Automation ConferenceJune 1991 Pages 740–745https://doi.org/10.1145/127601.127762Published:01 June 1991Publication History 72citation503DownloadsMetricsTotal Citations72Total Downloads503Last 12 Months21Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A linear time-complexity algorithm for lossy transmission line simulation within arbitrary nonlinear circuits is presented. The method operates by storing information about the state of the line at dynamically selected internal points and using an analytical formulation based on impulse responses to predict the line's future behavior accurately. Previous approaches using impulse responses possess quadratic-time complexity. The proposed method does not require rational or other approximations of transfer functions to achieve linear time-complexity, nor does it increase the size of the simulator's matrix by more than 2 for each transmission line. Experimental results on industrial circuits indicate that, for equivalent or superior accuracy, the state-based method can be faster for simulations of one or more block or data pulses, with speedups of more than 10 and 50 over the convolution and lumped-RLC methods for the longer simulations.>