This paper deals with management issues on employees who are working apart the employer. Since the management activities are highly dependent on the supervisor's individual capabilities and performance, IT based managements are proposed for productivity improvement of employees working apart. Then, the Timed-PDCA concept, which has been developed for target achievements, is applied to the IT based management system. Some unique ideas for at-a-glance visualization of workers activities and report writing navigation for enforcing workers to seriously utilize their mind are presented.

In this paper, using an application software system called “sales funnel” is proposed to improve sales force performance measurement and training for B2B business. With this software, updating prospects' information weekly at the origin by sales representatives, allows real time sharing of information throughout a corporation and visualizing the entire sales process. This reduces data preparation time before corporate level strategic discussions. Enforcing weekly updates by this system results in time shortened PDCA (Plan, Do, Check, and Act) cycles, thereby enabling the acceleration of the sales activities. Moreover, repeated PDCA cycles with enforced logical thinking, gives essential on-the-job training to the sales representatives, nurturing them into becoming better performers.

A new data management method called “ISSEI” was proposed in the previous report [1], to avoid slowing down of data retrieving time for the database that has an inherent nature of ever growing data volume. The experimental evaluation showed that ISSEI had a significantly faster data retrieving time and required less CPU and RAM usages in the database server. This paper deals with additional evaluations of other data handling performances as the necessary steps towards a successful replacement of the conventional commercial DBMS by ISSEI. Experimental comparisons between MS SQL Server and ISSEI were conducted by changing the size of data volumes in the database, having revealed interesting results. One interesting result is that ISSEI shows faster updating and deleting time in large data volume sizes than MS SQL Server, but slower adding time in any data volume size than the MS SQL Server. Another interesting observed result is that while the MS SQL Server's performance depends on the size of the data volume to be handled at a time, ISSEI's performance shows no dependency on the data volume size. These two additional evaluation results are showing that the proposed ISSEI data management method has superiority in massive data handling over the conventional commercial DBMS.

A new concept of the computer icon is presented, whose roles are expanded to have all control functions for the object window from the very limited original roles to show merely the existence and the kind of the object. The “control” icon uses the push-pin icon that consists of a push-pin image and its shadow as proposed by the authors' previously [6,7]. The main subject of this paper is how to apply the new “control” icon concept to the MS Windows environment. The paper describes that the control icon realized as an add-on software program on the MS Windows can control any existing application programs without requiring modifications. Also, a new intuitive method for resizing the displayed object window with a free aspect ratio is presented.

This paper discusses possible assisting approaches with that the search engine indicates additional keywords for searching the desired documents after the first keyword is specified by the user. Effectiveness of a new idea to utilize a frequency distribution of terminologies used in all the database documents was evaluated, showing a promising indication that the approach is useful for suggesting good candidate terminologies for secondary keywords. The paper indicates necessary steps towards building of a more efficient search engine including establishment of a solid mathematical or statistical foundation for determining a group of meaningful terminologies from any arbitrary database, and combination with other approaches for augmenting searching performance.

This paper describes a unique collaborative system based on a knowledge database. First its functional mechanisms, typical usages by users and the merits observed over long-term internal testing are described in detail. Then, the issues to overcome barriers for handling massive and growing volumes of data are discussed, and a novel and promising data handling method that can be used in place of conventional DBMS is presented. Performance evaluations in an actual environment using the proposed method demonstrated drastic improvements.

Hardware implementation aspects of sophisticated speech codecs are addressed. The major points discussed are approaches to implementation of the sophisticated speech codecs, requirements for DSP (digital signal-processing) implementation of the codecs, such as the type of arithmetic processing and the necessity of bit-level specifications, and codec implementation and DSP programming techniques for three specific coding algorithms: 32-kb/s ADPCM (adaptive digital pulse code modulation), 64-kb/s (7 kHz) SB (subband)-ADPCM, and 16-kb/s APC-AB (adaptive predictive coding with adaptive but allocation) codecs.>

Three kinds of encoder configurations, which include noise shaping, predictive and their combination forms, are investigated from LSI implementation points of view. A first order predictive encoder with first order noise shaping is chosen. A novel circuit configuration for the selected structure is proposed, which consists of a digital predictor with a capacitor array D-to-A converter, an operational amplifier and a comparator. The configuration can greatly decrease step unbalance effect, settling time and output voltage swing requirements for the operational amplifier, and the number of analog components. These features are essential in fine pattern LSI implementation. Capacitor fabrication error effects on the signal-to-noise ratio are numerically analyzed. A simplified decimation filter realization, which needs no high speed multiplier, is introduced.

The synchronous tandem property of nonaccumulation of distortion in tandem-connected ADPCM coders with a 64 kbit/s PCM interface is discussed here. The synchronous tandem algorithm used to provide this property in the steady-state mode is described with a case-by-case analysis, so as to show how the synchronous tandem property is realized in an ADPCM coder. A 32 kbit/s ADPCM coder utilizing this algorithm has been standardized by the CCITT (International Telegraph and Telephone Consultative Committee). The synchronous tandem property of the 32 kbit/s ADPCM coder is of great interest in network applications, because the ADPCM coder appears likely to be introduced into digital networks built partially with existing 64 kbit/s PCM circuits.

An ADPCM codec, that can provide toll quality speech at a 32 kb/s transmission rate, has been implemented on a single chip signal processor. Maximum effort has been paid to design a robust adaptation scheme for a quantizer and a predictor to withstand transmission bit errors. The codec employs a simplified robust quantizer and also employs a new backward adaptive predictor. The decoder, including the new adaptive predictor, has a structure having fixed poles and adaptive zeros, attaining both high prediction capability and robustness. The performance of a developed codec, which has analog interface capability through a PCM codec chip, satisfies the standard 64 kb/s PCM performance specification in CCITT recommendation G.712.

Two new digital transmultiplexers intended for commercial use have been developed. One transmultiplexer performs a bilateral conversion between two 12-channel FDM group signals and a 24-channel PCM carrier signal. The other mutually connects two 60Channel FDM supergroup signals and five 24-channel or four 30channel PCM signals. Both exploit a block processing digital SSBFDM multiplex/demultiplex scheme employing a cascade of an FFT processor and a set of complex coefficient digital filters. They have been built using newly developed high-level DSP LSI chips. Algorithmic considerations, developed LSI architecture, and equipment configuration are described as well as digital processor design details and measured performance.

This paper describes a new LSI chip set developed to provide a simple and cost-effective means for DSP hardware implementation. This chip set, consisting of two NMOS LSIs, contains enough logic and memory to perform such high level DSP functions as biquad filters and FFT butterflies at a high throughput rate, without any other external logic devices. It employs serial arithmetic and operates at a clock rate up to more than 5 MHz. Throughput rate can be traded-off with processing accuracy. Architecture is designed to pursue self-sufficient applicability to high level DSP functions, while retaining generality in application.

The development of a microprocessor-controlled 96/48 DSI terminal is described. The terminal is intended for domestic use, and is designed so as to maximize compatibility with existing digital carrier systems, it merges four T1 signals into two T1 compatible bit streams for transmission. The terminal is given sufficient excess capacity to accommodate voiceband data, while retaining toll-grade transmission quality for speech. Implementation approaches and considerations in both calculated and measured system characteristics are described.

A single chip, versatile digital signal processor has been developed, which enables compact and low cost telecommunications equipment realization. The processor architecture has been optimized for real time voiceband signal processing by adopting efficient micro-program control and by integrating a 16 × 16 bit parallel multiplier on a single chip. The processor is fabricated with N-channel MOS technology, and operates at a clock speed up to more than 8 MHz. Any instruction, including multiplication, can be performed within a 250 nanosecond interval. The paper also describes applications to actual voiceband communications equipment to prove the processor effectiveness.

A 120-channel transmultiplexer has been developed which interfaces two FDM basic supergroup signals (2 x 60 channels) directly to the digital time division switch or digital transmission systems. The equiplnent exploits a block processing digital SSB-FDM multiplex/demultiplex scheme, and has been built using newly developed high-speed CMOS pipeline multipliers and variable length shift registers. System design considerations and hardware implementation techniques are described in detail as well as the measured performance.

A new alternative to PCM framing system implementation is presented, which exploits LSI memories for performance improvement and hardware simplification. The proposed system simply consists of a tapped delay line for simultaneous observation of multiple framing bits and an ROM programmed sequence controller for framing system operation. Application to D3 format PCM signals is described in detail. Performance analyses, made by using signal flow graphs, show that the approach presented here is a superior alternative to the conventional approach.

A new method for digital implementation of SSB-FDM modulation and demodulation is presented, which utilizes the FFT algorithm to reduce the multiplication rate. The hardware realization of the presented method is shown to be the simplest; it consists of only an FFT processor and a set of complex bandpass filters which operate at the same rate as the input baseband sequences; no signal conversions are required prior to FFT processing. Simple and practical approaches are presented for design and implementation of the EFT processor and the set of complex bandpass filters. Design examples, which are made for implementation of a TDM-FDM translator at the supergroup level, show that the proposed method can attain the minimum multiplication rate among methods previously reported.