In this paper, we develop a logic synthesis approach which relies on accurate design evaluation program to estimate the final design attributes such as layout speed. Given a candidate design implementation, an evaluation program is called upon to provide quick and accurate estimates of the critical path delay. This information is then used as a feedback to the logic optimization system. Based on this feedback, the system will "re-orient" itself toward a new direction for optimization. Such a scheme represents a more realistic way of generating optimal layout implementations.>

The complexity of circuit designs has necessitated a top-down approach to layout synthesis. A large body of work shows that a good layout hierarchy, or partitioning tree, as measured by the associated Rent parameter, will correspond to an area-efficient layout. We define the intrinsic Rent parameter of a netlist to be the minimum possible Rent parameter of any partitioning tree for the netlist. Experimental results show that spectra-based ratio cut partitioning algorithms yield partitioning trees with the lowest observed Rent parameter over all benchmarks and over all algorithms tested. For examples where the intrinsic Rent parameter is known, spectral ratio cut partitioning yields a partitioning tree with Rent parameter essentially identical to this theoretical optimum. These results have deep implications with respect to both the choice of partitioning algorithms for top-down layout, as well as new approaches to layout area estimation. The paper concludes with directions for future research, including several promising techniques for fast estimation of the (intrinsic) Rent parameter.>

We discuss the problem of accurate delay estimation of cell-based designs, prior to any physical design tasks. For this purpose, we require accurate wire-length estimates, since wire delays contribute significantly to the overall delay. We present a new technique for wire-length estimation based on a combination of analytical and constructive approaches. Given these wire-length estimates and the cell delays, it is possible to provide worst case delay paths in the design based on the circuit topology. We have also extended our technique to consider false paths, which provides a more accurate functionality based estimate that takes into account the estimated layout information. We validate our technique using the standard MCNC benchmarks. Our results indicate an average 7% accuracy in the worst case delay predictions for designs with up to about 2800 cells.>

The authors address the problem of evaluating area tradeoffs for VLSI layouts from high-level specifications (typically register-transfer level). An area prediction approach based on two models, analytical and constructive, are presented. A circuit design is partitioned recursively down to a level specified by the user, thus generating a slicing tree. An analytical model is then used to predict the shape function of each of the leaf subcircuits. By traversing the tree in post-order, the shape function of the entire layout design can be predicted constructively. This approach also permits the user to trade off the accuracy of the prediction versus the runtime of the predictor. Such a scheme is quite useful for high level design tasks. The authors show experimentally that the estimates obtained using this model are within 5% of the actual layout area for designs ranging from 125 to 12000 cells.>

The problem of estimating design quality measures to accurately reflect design tradeoffs and efficiently explore the design space is discussed. Specifically, interest is centered on predicting the layout area and delay of a given structural RT level design. Clearly, current RT level cost measures are highly simplified and do not reflect the real physical design. In order to establish a more realistic assessment of layout effects, a layout model which accurately and efficiently accounts for the effects of wiring and floorplanning on the area and performance layout of RT level designs is proposed. Benchmarking has shown that this model is quite accurate.>