The RRAM-based accelerators have become very popular candidates for neural network acceleration due to they perform matrix-vector multiplication in-memory with high storage density and low latency. Many related works have used fixed-precision quantization to achieve the model compression and enhance the tolerance of process variation, but these methods still suffer a large accuracy degradation and poor robustness to nonideal effects. In this work, we propose a crossbar-aware mixed-precision quantization scheme, which enables to search for the optimal precision of each part of the network as a way to improve the accuracy and robustness to noise. First, we introduce a group quantization strategy that can flexibly adjust the group size dynamically according to the crossbar size. Then, we propose a detailed mixed-precision search flow to search for the optimal precision set of the network. Finally, we give a noise injection adaption training method to enhance the tolerance of noise. Experimental results show that our proposed method can improve inference accuracy by at least 2.04% compared to the fixed-precision quantization under the same resource cost. The searched architecture with the highest accuracy most accurate (MA) could achieve an accuracy of 92.39% and a resource saving of 93.30% compared to the full precision model. The searched architecture with the biggest resource savings most efficient (ME) could achieve an accuracy of 91.11% and a resource saving of 95.57% compared to the full precision model. And, the average precision of the ME mixed-precision architecture is only 1.4 bits. Besides, the results show the mixed-precision network with noise adaption training is more robust to noise than the fixed-precision network with noise adaption training.

In-memory computing based on memristor has attracted significant interest in order to break the von Neumann computer architecture's data-transfer bottleneck and develop high-efficient computing systems. Memristor- based logic gate is one of the potential ways to achieve these goals. Recently, there are many methods which have been presented to achieve Boolean functions, such as material implication (IMP). IMP logic gate consists of two parallel memristors, which can achieve IMP logic operation by applying appropriate voltages to memristors. With the help of IMP logic gate's structure, we could achieve many other Boolean functions by applying different voltages. We deduce the formulas which represent the relationships between applied voltages and memristors' resistances based on IMP logic gate's structure for achieving other Boolean functions. And according to these formulas, we design the schemes of applying voltages and demonstrate these designs with SPICE simulation. In addition to this, the new structure which consists of two antiparallel memristors is taken into consideration. Similarly, based on it, we deduce the formulas and design the schemes of applying voltages and demonstrate these with SPICE simulation.

Memristor-based stateful logic demonstrates a method of in-memory computing, which is a promising way to overcome the data-transfer bottleneck in the current von Neumann computer architecture. However, due to the instability, the memristor device exhibits an inherent stochastic switching behavior especially when the applied voltage is in the switching range of unsafe writing. In such case, the delicate design of stateful memristor gates could suffer the reliability problem. Here, such unsafe writing impacts on the memristor-based logic operation is systematically analyzed. Through establishing the Markov chain model of unsafe writing effects, we deduce the mathematical relationship between the material implication (IMP) logic gate reliability and switching probability. It reveals that unsafe writing with enough operation time would make the IMP logic converge to always True logic. The best operation time for the unsafe write is then proposed to improve the probability of right logic function and avoid the undesired logic result, which is demonstrated with simulation.

Recent years, several memristor-based neuromorphic processing chips have been proposed. However, there is few architectures to consider the cascading problems, and the scalability is not strong while dealing some tasks. To address this issue, we present a memristor-based cascaded method with some basic computation unit, several neural network processing chips can be cascaded by this means to improve the processing capability of the dataset. Compared with VGGNet and GoogLeNet, the proposed cascaded framework can achieve 93.54% Fashion-MNIST accuracy under the 4.15M parameters. Extensive experiments are conducted show that the circuit simulation results can still provide a high recognition accuracy, the recognition accuracy loss after circuit simulation can be controlled at around 0.26%.

With the rapid development of VLSI industry, the research of intelligent applications moves towards IoT edge computing. While the power consumption and area cost of deep neural networks usually exceed the hardware limitation of edge devices. In this paper, we propose a low-power neural network architecture to address such problem. We simplify the current popular convolutional neural networks structure, and utilize the memristor crossbar to store weights to execute convolution operation in parallel, and we present the spiking convolutional neural networks. At the same time, we proposed a performance metrics V to help provide design guidelines for choosing the parameters of the network.