Disk I/O is increasingly the performance bottleneck in computer systems despite rapidly increasing disk data transfer rates. In this article, we propose Automatic Locality-Improving Storage (ALIS), an introspective storage system that automatically reorganizes selected disk blocks based on the dynamic reference stream to increase effective storage performance. ALIS is based on the observations that sequential data fetch is far more efficient than random access, that improving seek distances produces only marginal performance improvements, and that the increasingly powerful processors and large memories in storage systems have ample capacity to reorganize the data layout and redirect the accesses so as to take advantage of rapid sequential data transfer. Using trace-driven simulation with a large set of real workloads, we demonstrate that ALIS considerably outperforms prior techniques, improving the average read performance by up to 50% for server workloads and by about 15% for personal computer workloads. We also show that the performance improvement persists as disk technology evolves. Since disk performance in practice is increasing by only about 8% per year, the benefit of ALIS may correspond to as much as several years of technological progress.

As improvements in processor performance continue to far outpace improvements in storage performance, I/O is increasingly the bottleneck in computer systems, especially in large database systems that manage huge amoungs of data. The key to achieving good I/O performance is to thoroughly understand its characteristics. In this article we present a comprehensive analysis of the logical I/O reference behavior of the peak productiondatabase workloads from ten of the world's largest corporations. In particular, we focus on how these workloads respond to different techniques for caching, prefetching, and write buffering. Our findings include several broadly applicable rules of thumb that describe how effective the various I/O optimization techniques are for the production workloads. For instance, our results indicate that the buffer pool miss ratio tends to be related to the ratio of buffer pool size to data size by an inverse square root rule. A similar fourth root rule relates the write miss ratio and the ration of buffer pool size to data size. In addition, we characterize the reference characteristics of workloads similar to the Transaction Processing Performance Council (TPC) benchmarks C (TPC-C) and D(TPC-D), which are de facto standard performance measures for online transaction processing (OLTP) systems and decision support systems (DSS), respectively. Since benchmarks such as TPC-C and TPC-D can only be used effectively if their strengths and limitations are understood, a major focus of our analysis is to identify aspects of the benchmarks that stress the system differently than the production workloads. We discover that for the most part, the reference behavior of TPC-C and TPC-D fall within the range of behavior exhibited by the production workloads. However, there are some noteworthy exceptions that affect well-known I/O optimization techniques such as caching (LRU is further from the optimal for TPC-C, while there is little sharing of pages between transactions for TPC-D), prefetching (TPC-C exhibits no significant sequentiality), and write buffering (write buffering is lees effective for the TPC benchmarks). While the two TPC benchmarks generally complement one another in reflecting the characteristics of the production workloads, there remain aspects of the real workloads that are not represented by either of the benchmarks.

Recent developments in both hardware and software have made it worthwhile to consider embedding intelligence in storage to handle general-purpose processing that can be off-loaded from the hosts. In particular, low-cost processing power is now widely available and software can be made robust, secure and mobile. In this paper, we propose a general smart storage (SmartSTOR) architecture in which a processing unit that is coupled to one or more disks can be used to perform such off-loaded processing. A major part of the paper is devoted to understanding the performance potential of the SmartSTOR architecture for decision support workloads. Our analysis suggests that there is a definite performance advantage in using fewer but more powerful processors, a result that bolsters the case for sharing a powerful processor among multiple disks. As for software architecture, we find that the off-loading of database operations that involve only a single relation is not very promising. In order to achieve significant speed-up, we have to consider the off-loading of multiple-relation operations. In general, if embedding intelligence in storage is an inevitable architectural trend, we have to focus on developing parallel software systems that can effectively take advantage of the large number of processing units that will be in the system.

There are two concurrent paths in a typical cache access --- one through the data array and the other through the tag array. The path through the data array drives the selected set out of the array. The path through the tag array determines cache hit/miss and, for set-associative caches, selects the appropriate line from within the selected set. In both directmapped and set-associative caches, the path through the tag array is significantly longer than that through the data array. In this paper, we propose a path balancing technique to help match the delays of the tag and data paths. The basic idea behind this technique is to employ a separate subset of the tag array to decouple the one-to-one relationship between address tags and cache lines so as to achieve a design that provides higher performance. Performance evaluation using both TPC-C and SPEC92 benchmarks shows that this path balancing technique offers impressive improvements in overall system performance over conventional cache...

There has been a wealth of research in the area of parallel join algorithms. Among them, hash-based algorithms are particularly suitable for shared-nothing database systems. The effectiveness of these techniques depends on the uniformity in the distribution of the join attribute values. When this condition is not met, a severe fluctuation may occur among the bucket sizes, causing uneven workload for the processing nodes. Many parallel join algorithms with load balancing capability have been proposed to address this problem. Among them, the sampling and incremental approaches have been shown to provide an improvement over the more conventional methods. The comparison between these two approaches, however, has not been investigated. In this paper, we improve these techniques and implement them on an nCUBE/2 parallel computer to compare their performance. Our study indicates that the sampling technique is the better approach.>

The pipelined execution of multijoin queries in a multiprocessor-based database system is explored in this paper. Using hash-based joins, multiple joins can be pipelined so that the early results from a join, before the whole join is completed, are sent to the next join for processing. The execution of a query is usually denoted by a query execution tree. To improve the execution of pipelined hash joins, an innovative approach to query execution tree selection is proposed to exploit segmented right-deep trees, which are bushy trees of right-deep subtrees. We first derive an analytical model for the execution of a pipeline segment, and then, in the light of the model, we develop heuristic schemes to determine the query execution plan based on a segmented right-deep tree so that the query can be efficiently executed. As shown by our simulation, the proposed approach, without incurring additional overhead on plan execution, possesses more flexibility in query plan generation, and can lead to query plans of better performance than those achievable by the previous schemes using right-deep trees.>

Modern, high-performance processors employ techniques such as superscalar execution and super-pipelining to increase their instruction issue rate. As the instruction issue rate of processors increases, however, the negative impact of branches on performance also increases. This paper describes an instruction cache (I-cache) prefetch mechanism to improve processor performance on the taken branches. Under perfect conditions, the mechanism allows the target of a taken branch to be prefetched early enough to completely hide the memory latency of an I-cache miss.>

When the work involved in a join is partitioned among multiple processors in the parallel join, the skew in the operand relations can result in significant imbalance in the work assigned to the different processors. This imbalance can cause significant degradation in the response time for the join operation.

It is shown that the fragment and replicate (FR) distributed join algorithm is a special case of the symmetric fragment and replicate (SFR) algorithm, which improves the FR algorithm by reducing its communication. The SFR algorithm, like the FR algorithm, is applicable to N-way joins and nonequijoins and does tuple balancing automatically. The authors derive formulae that show how to minimize the communication in the SFR algorithm, discuss its performance on a parallel database prototype, and evaluate its practicality under various conditions. It is claimed that SFR improves the worst-case cost for a distributed join, but it will not displace specialized distributed join algorithms when the later are applicable.>

Garcia-Molina, Lipton, and Valdes [1] introduced a new machine architecture called "massive memory machines" (MMM). The primary application of their proposed architecture was for so-called memory bound computations. In this correspondence we argue: 1) that massive memories will likely become feasible, but will be most effective with much more powerful processors, and 2) that a massive memory on the proposed machine will perform poorly in the same cases that virtual memory performs poorly: whenever there is poor locality of memory reference. Other problems with the architecture are also discussed. These related issues include: 1) the infeasibility of large on-chip dual port memory, 2) the support of multiprocessing on an ESP, 3) the possibility of memory prerequest, 4) the potential of trading program size for execution time, and 5) the time required for clearing the entire memory.

article Free Access Share on PIPE: a VLSI decoupled architecture Authors: J. R. Goodman The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Jian-tu Hsieh The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Koujuch Liou The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Andrew R. Pleszkun The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , P. B. Schechter The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile , Honesty C. Young The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WI The University of Wisconsin-Madison, Computer Sciences Department, 1210 W. Dayton St., Madison, WIView Profile Authors Info & Claims ACM SIGARCH Computer Architecture NewsVolume 13Issue 3June 1985 pp 20–27https://doi.org/10.1145/327070.327117Published:01 June 1985Publication History 101citation592DownloadsMetricsTotal Citations101Total Downloads592Last 12 Months50Last 6 weeks13 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF