Delay testing is a technique to determine if a chip will function correctly at a specified frequency. If a chip passes delay tests, it will presumably function at the specified frequency in the field. This paper presents experimental results that show how chips can pass very thorough delay tests and still fail in the field. It is shown that some chips sometimes pass and sometimes fail when the same delay test is applied multiple times under the same test conditions. These chips are called inconsistent fails. This paper shows how tester timing edge placement accuracy can cause inconsistent fails and suggests the minimum requirements for guardbands that avoid the inconsistent test results.

This paper presents segmented addressable scan (SAS), a test architecture that addresses test data volume, test application time, test power consumption, and tester channel requirements using a hardware overhead of a few gates per scan chain. Using SAS, this paper also presents systematic scan reconfiguration, a test data compression algorithm that is applied to achieve 10× to 40× compression ratios without requiring any information from the automatic-test-pattern-generation tool about the unspecified bits. The architecture and the algorithm were applied to both single stuck as well as transition fault test sets.

Often times a particular research topic is the result of a group of individuals working together to better characterize or solve a current problem. It can be beneficial for the group of researchers to present their research and early-stage results to fellow engineers to obtain input that may help direct their research efforts. The Special Session "Elevator Talks" provides a forum for 15 researchers to each make a 4 minute presentation (plus a 1 minute question period) on an emerging research topic and key results of this research. The work described in the "Elevator Talks" is new research that has not been presented at any other confe

This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consumption, and tester channel requirements. With minimal hardware overhead, the architecture provides at least an order of magnitude reduction to each of the above problems. The architecture relies on scan chain segmentation and multiple-hot decoders.

The cost of FPGA manufacturing test is driven by the number of test configurations and the time required to configure an FPGA under test. The high degree of regularity of an FPGA, which is an array of interconnected logic blocks, results in manufacturing test configurations that are also highly regular. Subframe multiplexing takes advantage of the regularity in test configurations to greatly reduce the configuration time, the dominant portion of the test time. This design for test technique requires only a minor modification to the existing configuration hardware---the addition of several two-bit multiplexers---while maintaining the same configuration memory architecture. Results are shown for Xilinx Virtex and Virtex-E series FPGAs, yielding a configuration time reduced by several orders of magnitude compared to the best current technique.

FPGA test cost can be greatly reduced by minimizing the number of test configurations. A test technique is presented for FPGAs with multiplexer-based routing architectures in which multiple logical paths through each multiplexer is enabled instead of only one path. It is shown that for Xilinx Virtex-II and Spartan-3 FPGAs only 8 test configurations are required to achieve 100% stuck-at, PIP stuck-on, and PIP stuck-off fault coverage.

Standard I/sub DDQ/ testing is limited by the ability to distinguish a small fault current from a large background leakage current: this limitation is overcome in FPGAs by differential I/sub DDQ/ testing. Partitioning of interconnects further increases the detectability of a fault current. Fault location can be achieved by iteratively applying partitioned differential I/sub DDQ/ testing to eliminate fault-free nets. The location algorithm, easily automated, requires very few configurations and I/sub DDQ/ measurements, logarithmic to the number of initially-suspected faulty nets.

Interconnection networks consume the majority of the die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple delay and/or bridging interconnection faults. This method achieves an adjustable, maximum sensitivity to resistive open defects of several kilo-ohms. Bridging faults modeled as either wired-AND or wired-OR are detectable. Finally, fast and simple fault localization is presented.