Sun's T2 processor transition test methodology, verification and silicon debug are described. We illustrate our test mechanism, test sequence, test development, and the verification of this mechanism in silicon. Methods to identify slow flops, diagnose gate dominated paths, excite long delay for wire dominated paths, and find essential patterns for speed characterization are presented. In addition, a method is developed for recovering devices with a fewer good processor cores. All these applications together make transition test a much more powerful tool.

Testing of one-dimensional (1-D) unilateral iterative logic arrays (ILA's) of combinational cells with constant test vectors is studied and the concept of one repetition length (ORL) within the tests used for testing C-testable arrays is described. The impact of ORL on the test set size and the design of the test generator are discussed. ORL can dramatically reduce the on-chip test generator size with a negligible increase in the test set size. ORL, coupled with a single distinguishing sequence (DS) for ILA's with cell vertical outputs has proved to be attractive in terms of both reduced test set size and reduced test generator size. ORL testability can be used for C-testable arrays with single faulty cell and multiple faulty cells. The technique for using a single linear finite state machine (LFSM) for generating the necessary deterministic test patterns followed optionally by pseudorandom patterns from the same automaton is discussed. Use of an LFSM as a built-in test generator for only deterministic tests for 1-D ILA's is covered. With ORL, a compact LFSM based built-in self test (BIST) generator can deliver the test vectors to all the cells in the array. The exact probability distribution equation has been developed for additional bits needed to map a nonlinear machine (FSM) definition into a LFSM definition. The distribution clearly shows that the expected number of additional bits is very small, often zero.>

Linear Finite State Machine for One Dimensional (1D) Iterative Logic Arrays (ILAs) is described. The technique for modifying the Linear Feedback Shift Register (LFSR) based test generator called Linear Finite State Machine (LFSM) for deterministic test pattern generation is discussed and extended for generating the test vectors for 1D unilateral ILAs. One Repetition Length (ORL) of C-testable ILAs and unique characteristics of the C-testable test patterns are used for the compact design of the LFSM based at-speed Built-in Self Test (BIST). Such LFSM based BIST occupies small silicon area, simplifies the design of the controller and does at-speed testing of the ILAs. This results in reduced time and cost of testing. In addition, the exact probability distribution equations are developed for additional bits needed to map a Finite State Machine (FSM) into an LFSM. The distribution clearly shows that the expected number of additional bits is very small, often zero. The probability distribution equations are equally valid for any LFSR based test generator for other circuits.>

Testing of one dimensional unilateral iterative logic arrays (ILAs) of combinational cells under multiple faults is discussed. It has been shown that it is possible to generate a test set for ILAs with primary outputs under multiple faults. Some ILAs have a constant number of test vectors independent of the size of the array. These types of arrays are called C-testable arrays. Present work proves that all useful one dimensional unilateral ILAs with only boundary outputs are not C-testable under multiple faults.>

A deterministic test pattern generator for BIST, based on linear feedback shift registers is discussed. A method of designing the test pattern generator in order that it generates deterministic as well as pseudo random patterns is presented. One application of this method is illustrated where deterministic at-speed testing of C-testable ILAs, covering all possible single and multiple combinational faults is achieved. Response analysers are discussed including one with zero aliasing probability. The algorithms for synthesizing the small amount of BIST hardware are explained.>