In a standard workflow for the validation of a control system, the control system is implemented as an extension to a simulator. Such simulators are complex software systems, and engineers may unknowingly violate constraints a simulator places on extensions. As such, errors may be introduced in the implementation of either the control system or the simulator leading to invalid simulation results. This paper presents a novel runtime verification approach for verifying control system implementations within simulators. The major contribution of the approach is the two-tier specification process. In the first tier, engineers model constraints using a domain-specific language tailored to modeling a controller's response to changes in its input. The language is high-level and effectively hides the implementation details of the simulator, allowing engineers to specify design-level constraints independent of low-level simulator interfaces. In the second tier, simulator developers provide mapping rules for mapping design-level constraints to the implementation of the simulator. Using the rules, an automated tool transforms the design-level specifications into simulator-specific runtime verification specifications and generates monitoring code which is injected into the implementation of the simulator. During simulation, these monitors observe the input and output variables of the control system and report changes to the verifier. The verifier checks whether these changes follow the constraints of the control system. We describe application of this approach to the verification of the constraints of an HVAC control system implemented with the power grid simulator Grid LAB-D.

Since APL, reductions and scans have been recognized as powerful programming concepts. Abstracting an accumulation loop (reduction) and an update loop (scan), the concepts have efficient parallel implementations based on the parallel prefix algorithm. They are often included in high-level languages with a built-in set of operators such as sum, product, min, etc. MPI provides library routines for reductions that account for nearly nine percent of all MPI calls in the NAS Parallel Benchmarks (NPB) version 3.2. Some researchers have even advocated reductions and scans as the principal tool for parallel algorithm design.Also since APL, the idea of applying the reduction control structure to a user-defined operator has been proposed, and several implementations (some parallel) have been reported. This paper presents the first global-view formulation of user-defined scans and an improved global-view formulation of user-defined reductions, demonstrating them in the context of the Chapel programming language. Further, these formulations are extended to a message passing context (MPI), thus transferring global-view abstractions to local-view languages and perhaps signaling a way to enhance local-view languages incrementally. Finally, examples are presented showing global-view user-defined reductions "cleaning up" and/or "speeding up" portions of two NAS benchmarks, IS and MG. In consequence, these generalized reduction and scan abstractions make the full power of the parallel prefix technique available to both global- and local-view parallel programming.

This paper describes an integrated architecture, compiler, runtime, and operating system solution to exploiting heterogeneous parallelism. The architecture is a pipelined multi-threaded multiprocessor, enabling the execution of very fine (multiple operations within an instruction) to very coarse (multiple jobs) parallel activities. The compiler and runtime focus on managing parallelism within a job, while the operating system focuses on managing parallelism across jobs. By considering the entire system in the design, we were able to smoothly interface its four components. While each component is primarily responsible for managing its own level of parallel activity, feedback mechanisms between components enable resource allocation and usage to be dynamically updated. This dynamic adaptation to changing requirements and available resources fosters both high utilization of the machine and the efficient expression and execution of parallelism.

Article Software prefetching Share on Authors: David Callahan View Profile , Ken Kennedy View Profile , Allan Porterfield View Profile Authors Info & Claims ASPLOS IV: Proceedings of the fourth international conference on Architectural support for programming languages and operating systemsApril 1991 Pages 40–52https://doi.org/10.1145/106972.106979Online:01 April 1991Publication History 394citation1,868DownloadsMetricsTotal Citations394Total Downloads1,868Last 12 Months79Last 6 weeks7 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

We present a graph coloring register allocator de-signed to minimize the number of dynamic memory references. We cover the program with sets of blocks called tiles and group these tiles into a tree reflecting the program’s hierarchical control structure. Registers are allocated for each tile using standard graph coloring techniques and the local allocation and conflict information is passed around the tree in a two phase algorithm. This results in an allocation of reg-isters that is sensitive to local usage patterns while retaining a global perspective. Spill code is placed in less frequently executed portions of the program and the choice of variables to spill is based on usage pat-terns between the spills and the reloads rather than usage patterns over the entire program. 1

Article Free Access Share on The Tera computer system Authors: Robert Alverson Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile , David Callahan Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile , Daniel Cummings Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile , Brian Koblenz Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile , Allan Porterfield Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile , Burton Smith Tera Computer Company, Seattle, Washington Tera Computer Company, Seattle, WashingtonView Profile Authors Info & Claims ICS '90: Proceedings of the 4th international conference on SupercomputingJune 1990 Pages 1–6https://doi.org/10.1145/77726.255132Online:01 June 1990Publication History 553citation2,281DownloadsMetricsTotal Citations553Total Downloads2,281Last 12 Months382Last 6 weeks81 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Most conventional compilers fail to allocate array elements to registers because standard data-flow analysis treats arrays like scalars, making it impossible to analyze the definitions and uses of individual array elements. This deficiency is particularly troublesome for floating-point registers, which are most often used as temporary repositories for subscripted variables.

Understanding synchronization is important for a parallel programming tool that uses dependence analysis as the basis for advising programmers on the correctness of parallel constructs. This paper discusses static analysis methods that can be applied to parallel programs with event variable synchronization. The objective is to be able to predict potential data races in a parallel program. The focus is on how dependencies and synchronization statements inside loops can be used to analyze complete programs with parallel loop and parallel case style parallelism.

The data cache performance of a set of computationally intensive programs is examined. The measurement of cache performance arises from an interest in improving the performance of a program during compilation. It was observed that the data caches contained the values for between 45% and 99+% of the array access, depending on the cache and the program. The delays from the misses accounted for up to half of the total execution time of the program. The misses were grouped in a subset of source program references which resulted in misses on every access. It is pointed out that aggressive compilers should be able to improve program performance by focusing on those array accesses that result in cache misses.>

An algorithm for constructing a precise call multigraph for languages that permit procedure parameters, extending the method of B. Ryder (see ibid., vol.5, no.3, p.216-225 (1979)) for handling recursion, is presented. If it is assumed that there is a constant upper bound on the number of procedure parameters to any procedure in the program, then the algorithm is polynomial in the total number of procedures in the program.>

article Free Access Share on The program summary graph and flow-sensitive interprocedual data flow analysis Author: D. Callahan Rice Univ., Houston, TX Rice Univ., Houston, TXView Profile Authors Info & Claims ACM SIGPLAN NoticesVolume 23Issue 7July 1988 pp 47–56https://doi.org/10.1145/960116.53995Published:01 June 1988Publication History 108citation1,084DownloadsMetricsTotal Citations108Total Downloads1,084Last 12 Months81Last 6 weeks22 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

A collection of 100 Fortran loops used to test the effectiveness of an automatic vectorizing compiler is described. The results of compiling these loops using commercially available, vectorizing Fortran compilers on a variety of supercomputers, minisupercomputers, and mainframes are presented. The testing methodology and loop scoring are explored.>

An algorithm for transforming sequential programs into equivalent parallel programs is presented. The method concentrates on finding loops whose separate iterations can be run in parallel without syn-chronization. Although a simple version of the method can be shown to be optimal, the problem of generating optimal code when loop interchange is employed is shown to be intractable. These methods are implemented in an experimental translation system developed at Rice University. 1.