Current literature has identified several issues with centralized mobility management in 5G-based Intelligent Transportation Systems (ITS), where 5G-enabled vehicles are expected to exhibit varying mobility patterns. So, distributed mobility management (DMM), where control plane mobility anchors work in a distributed fashion, is of keen interest to current researchers. Although existing DMM solutions, such as distributed mobile IPv6 (DMIPv6), distributed proxy MIPv6 (DPMIPv6), distributed mobility management software defined networking (SDN-DMM), distributed routing (D-Routing), and their derivatives appear to work fine in evolving 5G-based ITS, they cannot be applied directly. Further, to gauge their adaptability to different ITS scenarios, a thorough investigation of their performances is very much needed. Our key contributions in this paper include investigating DMM issues in 5G-based ITS scenarios, porting DMM schemes in 5G ITS, and developing a Markov model to evaluate handoff performance. The results show that DMIPv6 and DPMIPv6 outperform SDN-DMM and D-Routing in terms of end-to-end delay and signaling cost, with the latter increasing delay by 6-23% and signaling cost by 135% and 78%, respectively. However, SDN-DMM and D-Routing excel in packet loss ratio (15-20% lower), throughput (20-25% higher), and packet delivery cost (40% lower). In edge cloud flow mobility, SDN-DMM and D-Routing show better packet loss ratio as packet loss is caused by servers’ sensitive application delays rather than handoffs.

A novel hash-based hardware architecture for longest prefix match (LPM) scheme has been presented for IP processing.The main idea is to have zero false positive (+ve) rate with negligible false negative (-ve) rate. This has been achieved by implementing hardware-based simple hash functions for faster generation of routing table addresses. Prefix table has been designed using multiple read-port memory modules to deploy concurrent access of multiple memory words. Moreover, in this architecture, memory requirement has been reduced by maintaining next-hop address pointers instead of keeping actual next-hop address using global next-hop address memory. Prefix search time is fixed and restricts an LPM search operation within a single clock cycle irrespective of IPv4 and IPv6 address suits. This architecture can accommodate increased prefix growth trend of 40% – 100% with unchanged memory capacity. After rigorous testing, false -ve rate is found mostly zero and reasonably negligible (0.00512%) in worst-cases, however, false +ve rate is always zero. Lower bounds in memory requirements for four numerous schemes of the proposed LPM architecture with their probable failure-rates are analysed. System failure-rates are observed against incremental prefix growth with variable number of hash functions ranging from 6 to 8 to ensure future sustainability of the scheme.

With increasing use of runtime polymorphism and reliance on runtime type interpretation, the presence and importance of indirect branches has seen a considerable rise in recent workloads. Evidently, accurate target prediction for indirect branches has emerged as an important problem. While direction prediction of direct branches has received considerable research attention leading to efficient prediction policies and hardware structures implemented inside modern processors, proposals for target prediction for indirect branches has been relatively few. The problem of accurate target prediction for indirect branches is significantly tough since these transfer control to an address stored in a register that is known only at runtime. Unlike conditional direct branches, indirect branches can have more than two targets to be resolved at runtime, for which prediction requires a full 32-bit/64-bit address to be predicted, in contrast to just a taken or not-taken decision as needed for direction prediction of direct branches. Recent research shows indirect branches, being mispredicted more frequently, can start to dominate the overall branch misprediction cost. In modern processors, the only hardware structure available to facilitate target address prediction for indirect branches is a fixed-size Branch Target Buffer (BTB). BTB is often designed as a set associative cache for storing recent target addresses for branch instructions encountered during execution, with a motivation of being able to reuse the same addresses for future instances, thereby saving latency cycles. Evidently, designing efficient indexing schemes and replacement mechanisms for BTB structures is crucial, more so, for indirect branches, since these serve as the only prediction handle. In this paper, our objective is to examine a hierarchical BTB design for multicores with total size comparable to what exists today, with a motivation towards possible improvement of prediction accuracy by facilitating collaborative constructive learning between programs executing in different cores that encounter similar histories. Specifically, we wish to propose the concept of a small on-chip L1 BTB inside each core, supported by a larger off-chip L2 BTB shared among the cores. Our motivation towards a hierarchical BTB design is twofold. On one hand, in a multiprogramming environment, where the same program is executed in multiple cores, on different test cases, there is a significant potential of target information reuse for indirect branches, as is evident from our experiments on SPEC 2006 workloads. This is typically useful for machine learning based workloads where the training phase is often executed in different cores with the same neural network being trained on different training sets. On the other hand, with different programs in different cores, there is some chance of reuse as well, due to sharing of system libraries. The essence of our idea rests on the fact that programs executed in different cores have similar history patterns that can similarly influence the target addresses. Our design aims to decrease on the on-chip L1 BTB size while investing more storage for the off-chip shared L2 BTB. Suitable allocation and replacement policies support our hierarchical design. Initial experiments show expected accuracy benefits.

Network mobility (NeMo) arises when a mobile router connecting a network to the Internet dynamically changes its point of attachment. By taking advantage of this kind of network mobility, Internet services can be extended to users traveling in public transport vehicles having high speed LANs deployed on-board. On-board LANs connect to the Internet via mobile router. Here, two primary issues viz. mobility of the network as a hole and existence of multiple wireless links, give rise to several unique challenges for achieving a high end-to-end TCP throughput. In this paper we propose an approximately modified version of TCP Snoop, called on-board TCP (obTCP) for vehicular on-board IP networks. Its central concern is to shield the sender from non-congestion related losses without changing existing TCP implementation at the end hosts. We have evaluated the performance of obTCP in ns-2 simulator and compared with TCP Snoop