This paper presents a classification method for a Computer-Aided Diagnosis (CAD) system in a colorectal magnified Narrow Band Imaging (NBI) endoscopy. For the classification of a histologic findings, we consider an output result of a lesion endoscopic image from a pre-learned Convolutional Neural Network (CNN) as a feature vector and construct a set of Support Vector Machines (SVMs) by learning a set of the CNN feature vectors. In the video images, each frame has appearance changes such as blur, color shift, reflection of light and so on and it affects classification results. To improve the robustness of CAD system, we construct the SVM learned by multiple image sizes data sets so as to adapt to the noise peculiar to the video image. We confirmed that the proposed method achieves higher robustness, stable, and high classification accuracy in the endoscopic video image. The proposed method also can cope with differences in resolution by old and new endoscopes and perform stably with respect to the input endoscopic video image. We evaluated the proposed method on a customizable embedded DSP core implemented into a FPGA based prototyping system.

This paper presents a hardware implementation of a computer-aided diagnosis system that can classify lesions in real time for endoscopic video image. Unlike still images, video images contain many color shifts, blurs, reflections, and so on, a classification method that takes these noises into account is indispensable. In this paper, in the framework of Bag-of-Feature (BoF), we use a pre-learned convolutional Neural Network (CNN) with general images as feature extraction and Support Vector Machine (SVM) as classification. A robust classification method for endoscopic video is proposed by relearning SVM with several sets of endoscopic images. In addition, since CNN and SVM need to perform many multiplication and accumulation (MAC) operations, we implement the hardware system on a customizable DSP, which can be realize at high speed MAC operations and parallel processing with Very Long Instruction Word (VLIW). The prototyped system can be achieved real-time processing on video frame rate (30 fps @ 200 MHz). The proposed system enables not only to classify the presence or absence of cancer in the lesion but also to identify the progress of cancer and shows the clinical doctor as an objective indicator of the lesion in real time during the endoscopy examination.

In this paper, the computer-aided diagnosis system for colorectal endoscopic images is proposed. The proposed system is consisted of Convolutional Neural Network (CNN) as the feature extraction processing and Support Vector Machine (SVM) as identification processing. The proposed system is also implemented on customizable Digital Signal Processing (DSP) core: Vision P6 DSP and is demonstrated the effectiveness of a real-time recognition system by a FPGA based prototyping system, Protium™ S1.

We are going to develop an ultra-small nutrients analyzer, a compact 3D-monitor (shape, color, etc.), and an ultra-light environment sensor (light intensity, temperature, humidity, CO2, etc.), which can be installed near plants. Accordingly, plant growth estimation technologies based on micro-fluidic circuit model simulating plant vascular system are being developed. The model will be frequently corrected by using updated data given by those sensors. Furthermore, by making use of the estimation technologies, we try to find out suitable cultivation condition for producing plants having aimed characters. In this paper, in order to develop plant growth estimation technologies, we propose a method to analyze the growth of lettuce leaves and roots by image analysis based on visible and thermography thermal imagers captured by cameras in real time and non-destructive leaf and root growth in lettuce hydroponic culture.

This paper presents two iterative synthesis techniques between a high-level synthesizer (HLS) and the place and route tool to shorten the prolonged wire delay for a dynamically reconfigurable processor. At first, we use feedback wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on their congestions. The synthesis time was cut by 1/3 with only four points down on delay improvement rate.

In modern sub-micron design, achieving low-skew clock distributions is facing challenges for high-performance circuits. Symmetric global clock distribution and clock tree synthesis (CTS) for local clock optimization are used so far, but new methodologies are necessary as the technology node advances. In this paper, we study the register placement problem which is a key component of local clock optimization for highperformance circuit design along with local clock distribution. We formulate it as a minimum weighted maximum independent set problem on a weighted conflict graph and propose a novel efficient two-stage heuristic to solve it. To reduce the graph size, techniques based on register flipping and Manhattan circle are also presented. Experiments show that our heuristic can place all registers without overlaps and achieve significant improvement on the total and maximal register movement.

As the feature size of VLSI circuits scales down and clock rates increases, circuit performance is becoming more sensitive to process variations. This paper proposes an algorithm of symmetrical buffer placement in symmetrical clock trees to achieve zero-skew in theory, as well as robust low skew under process or environment variations. With the completely symmetrical structure, we can eliminate many factors of clock skew such as model inaccuracy, environment temperature and intra-die process variations. We devise a new dynamic programming scheme to handle buffer placement and wire sizing under the constraint of symmetry. By classifying the wires by tree levels and defining the level-dependent blockages, the potential candidate points in the gaps of circuit blocks can be fully explored. The algorithm is efficient for minimizing source-sink delay as well as other linear cost functions. Experiments show that our method helps to obtain a balanced design of clock tree with low delay, skew and power.

This paper describes a new hierarchical design method for large scale and high-performance LSIs, which eliminates the need to perform budgeting. The budgeting step in hierarchical design partitions the total propagation time constraint for a path between any two flip-flops (FFs) in different hierarchical blocks into budgets for the different segments of the path that lie within different blocks. In practice, budgeting may result in the need for additional iterations of the synthesis and physical design flow, or may achieve sub-optimal results in terms of area, power, or clock frequency. The proposed method makes the design process budgeting-free by moving the borders of the hierarchical blocks so that all borders of the hierarchical blocks are FFs. For a commercial 500 MHz LSI with 141 million transistors, the design team required 2 months to archive the target frequency through try-and-try-again budgeting, while our budgeting-free method produced a design that meets the performance target within days.

In this paper, we describe a design methodology and tools for NEC Electronics' structured ASIC, Instant Silicon Solution Platform (ISSP), which is being developed to fill the gap between FPGAs and standard cell-based ASICs. The ISSP has a unique regular-fabric architecture designed to achieve both a short time to production and high-performance LSI design. We have developed a special design methodology and tools to fully exploit the capability of this new device. Experimental results for industrial data show that our approach has advantages for ISSP design.

This paper examines the achievements and future of system-on-a-chip (SoC) design methodology and design flow from the viewpoints of an in-house electronic design automation team of an application-specific integrated circuit and system vendor. We initially discuss the problems of the design productivity gap caused by the SoC's complexity and the timing closure caused by deep-submicrometer technology. To solve these two problems, we propose a C-based SoC design environment that features integrated high-level synthesis (HLS) and verification tools. A HLS system is introduced using various successful industrial design examples, and its advantages and drawbacks are discussed. We then look at the future directions of this system. The high-level verification environment consists of a mixed-level hardware/software co-simulator, formal and semi-formal verifiers, and test-bench generators. The verification tools are tightly integrated with the HLS system and take advantage of information from the synthesis system. Then, we discusses the possibility of incorporating physical design features into the C-based SoC design environment. Finally, we describe our global vision for an SoC architecture and SoC design methodology.

This paper presents an efficient algorithm for buffered Steiner tree construction with wire sizing. Given a source and n sinks of a signal net, with given positions and a required arrival time associated with each sink, the algorithm finds a Steiner tree with buffer insertion and wire sizing so that the required arrival time (or timing slack) at the source is maximized. The unique contribution of our algorithm is that it performs Steiner tree construction buffer insertion, and wire sizing simultaneously with consideration of both critical delay and total capacitance minimization by combining the performance-driven A-tree construction and dynamic programming based buffer insertion and wire sizing, while tree construction and the other delay minimization techniques were carried out independently in the past. Experimental results show the effectiveness of our approach.

Presents a novel feed-through assignment algorithm based on minimum-cost multi-commodity flow formulation. After finding single-commodity flow with flow conflicts on the formulation, the algorithm eliminates all the conflicts to obtain a feasible solution. Since all nets and cell rows are considered simultaneously, our algorithm globally minimizes the number of tracks, the wire length, and the number of vias. Experimental results on benchmarks show that our algorithm substantially reduces these numbers compared with conventional algorithms.