The direct radio frequency power injection (DPI) method was extended using on-chip voltage waveform monitoring and built-in self-test techniques. Static random access memory (SRAM) has been chosen as a demonstrator of the extended DPI method and exhibits a higher susceptibility against the lower interference frequency. This response is explained when we consider the time length of the threshold against how long the supply voltage stays lower than the specific voltage determined for a SRAM core. This voltage is also found to be comparable but slightly smaller than the static voltage margin of SRAM cells. In-place measurements using the extended DPI provide an in-depth understanding of the susceptibility and help us to enhance the immunity of VLSI circuits.

This paper presents a decoupling capacitance boosting method for on-chip resonant supply noise reduction for DVS systems. The switching controls of decoupling capacitors depending on the supply noise states achieve an effective noise reduction and fast settling time simultaneously compared with the conventional passive decoupling capacitors. The measurement results of a test chip fabricated in a 0.18 μm CMOS technology show 12X boost of effective decap value, and 65.8% supply noise reduction with 96% settling time improvement.

Many of us in the field of ultra-low-Vddprocessors experience difficulty in assessing the sub/near threshold circuit techniques proposed by earlier papers. This paper investigates five major pitfalls which are often not appreciated by researchers when claiming that their circuits outperform others by working at a lower Vddwith a higher energy-efficiency. These pitfalls include: i) overlook the impacts of different technologies and different Vthdefinitions, ii) only emphasize energy reduction but ignore severe throughput degradation, or expect impractical pipelining depth and parallelism degree to compensate this throughput degradation, iii) unrealistically assume that memory's Vddand energy could scale as well as standard cells, iv) use the highest temperature as the worst timing corner as in the super-threshold, but in fact negative temperature becomes much more detrimental in the sub/near threshold regime, v) pursue just-in-need Vddto compensate effects of PVT, but without considering the high energy loss on DC-DC converters. Therefore, the actual energy benefit from using a sub/near threshold Vddcan be greatly overestimated. This work provides some design guidelines and silicon evidence to ultra-low-Vddsystems. The outlined pitfalls also shed light on future directions in this field.

For Dynamic Voltage Scaling (DVS), we propose a novel design methodology. This methodology is composed of an error detection circuit and three technologies to reduce the area and power penalties which are the large issues for the conventional DVS with error detection. The proposed circuit, Phase-Adjustable Error Detection Flip-Flip (PEDFF), adjusts the clock phase of an additional FF for the timing error detection, based on the timing slack. 2-Stage Hold-Driven Optimization (2-SHDO) technology splits the hold-driven optimization in two stages. Slack-Based Grouping Scheme (SBGS) technology divides each timing path into appropriate groups based on the timing slack. Slack Distribution Control (SDC) technology improves the sharp distribution of the path delay at which the logic synthesis tool has relaxed the delay. We evaluate the methodology by simulating a 32-bit microprocessor in 90 nm CMOS technology. The proposed methodology reduces the energy consumption by 19.8% compared to non-DVS. The OR-tree's latency is shortened to 16.3% compared to the conventional DVS. The area and power penalties for delay buffers on short paths are reduced to 35.0% and 40.6% compared to the conventional DVS, respectively. The proposed methodology with SDC reduces the energy consumption by 17.0% on another example with the sharp slack distribution by the logic synthesis compared to non-DVS.

Error Detection FFs for Dynamic Voltage Scaling (DVS) has been proposed. This technique controls the clock phase based on the timing slack, and reduces the energy consumption by 19.8% compared to non-DVS. The error signal latency is shortened to 6.3%, the area and power penalties for delay buffers on short paths become 35.0% and 40.6% lower compared to the conventional DVS.

The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%.

A single-chip data-driven microprocessor with special functions for distributed parallel processing is described. The implemented functions necessary for parallel processing are: relative addressing mode for program memory; efficient test and set operation of arbitrary data in data memory; transparent access of distributed shared memory; and dynamic load distribution among multiprocessors. With this microprocessor, practical parallel processing systems which exploit a wide area of scientific applications can be constructed.>