Application of multi-valued (non-binary) digital signals can provide considerable relief for a number of problems faced in binary systems, such as increased functional density and interconnection wirings. Heuristics have been used to synthesize multiple-valued logic (MVL) functions using near optimal number of product terms. In this paper, we explore the use of particle swarm optimization algorithm for synthesis of MV functions. The proposed approach was tested against 50000 randomly generated 2-variable 4-valued functions. The results show that the proposed algorithm outperforms other deterministic and ant colony based approaches in terms of the average number of product terms needed to synthesize a given MVL function.

With the increasing demand for high quality, more efficient, less area and less power circuits, the problem of logic circuit design has become a multiobjective optimization problem. Multiobjective optimization of logic circuits based on a fuzzified ant colony (ACO) algorithm is presented. The results obtained using the proposed algorithm are compared to those obtained using SIS in terms of area, delay and power for some known circuits. It is shown that the circuits produced by the proposed algorithm are better as compared to those obtained by SIS.

Evolutionary computation presents a new paradigm shift in hardware design and synthesis. According to this paradigm, hardware design is pursued by deriving inspiration from biological organisms. The new paradigm is expected to radically change the synthesis procedures in a way that can help discovering novel designs and/or more efficient circuits. In this paper, a multiobjective optimization of logic circuits based on a modified ant colony (ACO) algorithm is presented. The performance of the proposed algorithm is evaluated using a set of randomly generated circuits. The results obtained using the proposed algorithm are compared to those obtained using existing ACO-based techniques. It is shown that the designed circuits using the proposed algorithm outperform those of the existing techniques.

In this paper, the use of simulated evolution (SimE) algorithm in the design of digital logic circuits is proposed. SimE algorithm consists of three steps: evaluation, selection and allocation. Two goodness measures are designed to guide the selection and allocation operations of SimE. Area, power and delay are considered in the optimization of circuits. Results obtained by SimE algorithm are compared to those obtained by genetic algorithm (GA).

Mobile computing systems are used in different applications, some of which may be sensitive to be interrupted. However, these systems are susceptible to fault. One such fault is the failure of mobile support station. The main role of these stations is to help providing reliable and uninterrupted communication and computing facilities to mobile hosts. A scheme, known as the hybrid scheme, has recently been proposed that can tolerate failures of mobile support stations. The hybrid scheme combines the characteristics of two other schemes, known as pessimistic and optimistic schemes. There are two objectives that need to be optimized. These objectives are acknowledgement delay and storage capacity. We use fuzzy logic to find the best ratio of pessimistic to optimistic secondary stations to get the optimized values of the two objectives in the hybrid scheme. Simulation results show that fuzzy logic is a suitable choice for addressing the multiobjective nature of the problem.

The necessary and sufficient conditions for detecting transistor stuck-open faults in arbitrary multilevel CMOS circuits are shown. A method for representing a two-pattern test for detecting a single stuck-open fault using only one cube is presented. The relationship between the D-algorithm and the conditions for detecting transistor stuck-open faults in CMOS circuits is provided. The application of the proposed approach in robust test generation for transistor stuck-open faults in a number of benchmark circuits is demonstrated. The fault coverage achieved is as good as or better than those reported using existing techniques.

This paper presents a hardware-efficient memory allocation (EMA) technique designed to eliminate both internal and external fragmentation that appear in the buddy system. EMA can allocate a free memory block of any size in any part of memory. Hardware implementation of EMA is introduced, but only part of its circuits is shown in the paper due to the space limitation. Simulation results show that EMA utilizes memory space more efficiently than the previously known techniques.

This paper presents an elegant and efficient algorithm for detection of symmetry in Boolean functions represented by ordered binary decision diagrams (OBDDs).

A graph-based approach to finding near-optimal output phase assignments for PLA minimization is presented. A distinctive feature of the approach is that it exploits the necessary and sufficient conditions to reduce the number of product terms needed for PLA implementation and permits the use of existing graph algorithms to solve the PLA output phase optimization problem. The work is based on the transformation of a PLA into a graph whose vertices are the set of conditions required to reduce each product term of the PLA, and whose edges represent the relations between these conditions. Cliques (completely connected subgraphs) in the graph correspond to the output phase assignments required to reduce the product terms represented by the vertices in the cliques. The optimal PLA output phase assignment problem is then formulated as the well-studied problem in graph theory: finding maximum cliques in graphs. Using an existing algorithm for locating cliques in graphs, a modified greedy algorithm is proposed to compute output phase assignments for logic functions in polynomial time. Experimental results using a number of benchmark functions show that the graph-based approach can achieve optimal or near-optimal output phase assignment for PLA minimization and can lead to PLA's with fewer product terms than achieved using existing approaches.>

A new source of computational saving for test pattern generation, i.e., information reusing, is presented. The proposed technique can make full use of the pattern generation information from the last pattern to derive a set of new tests by means of critical path transitions. By so doing, fault propagation procedure is no longer required in the next pattern generation process and the line justification procedure is simplified. Experiments using the ISCAS-85 benchmark circuits show that when the technique is used with a deterministic test pattern generation algorithm (DTPG), computational cost is greatly reduced without a substantial increase in test length.>

Algorithms for synthesis of four-valued one- and two-variable functions for CCD (charge coupled device) implementation are proposed. One-variable synthesis is based on the observation that the cost of a realization of a function f(x) increases in the presence of breaks, or negative transitions, in the value of f as x increases. The function is decomposed to minimize the number of such transitions. Two-variable functions are synthesized as a sum of products of literals, taking advantage of literals that are easily implemented in CCD technology. It is concluded that the proposed algorithms perform better than those published previously.>

The cost effectiveness of using an overflow circuit for truncated difference operation and a metal line for charge replication in the charge-coupled device (CCD) realization of multivalue multithreshold (MVMT) functions is considered. It is shown that the use of these two circuits leads to improved realizations compared to those achieved by previous approaches.>

Basic multivalued building blocks constructed using CCD (charge-coupled devices) technology are presented. They are used to realize simple threshold functions. Existing techniques for decomposition of multivalued multithreshold functions into simpler subfunctions are reviewed. Usage of the CCD technology in implementation of these subfunctions is discussed. Two new decomposition techniques are proposed. Their aim is to obtain realizations that are better suited to CCD technology in terms of the maximum number of thresholds per element and the generation of negative weights. Synthesis techniques based on the proposed decompositions are presented and compared. Although 4-valued logic functions are stressed, the techniques are, in principle, applicable to functions of any radix.