Soft errors in Integrated Circuits (ICs) have always been a major concern, particularly as CMOS technology nodes continue to shrink, resulting in higher frequency, lower power, and smaller areas, exacerbating radiation-induced soft errors. Therefore, Single Event Transient (SET) has become a crucial consideration in designing modern radiation-tolerant circuits, as it has the potential to cause failures in circuit outputs. This paper employs the concept of signal probability for transient fault propagation in circuits. Considering the issue of transient fault-masking, an error propagation model is presented for each fault-masking case. Furthermore, approaches are proposed for both probabilistic and time-based scenarios to address the impact of re-convergent paths on transient error propagation. Since considering re-convergent paths increases computational complexity, three computational algorithms are proposed in this paper aiming to reduce the size of the probability matrix as much as possible. We compared the simulation results with the Monte-Carlo method and HSPICE-based simulation to validate the proposed method. According to the simulation results on ISCAS’85 benchmarks, the proposed approach for estimating the single event rate exhibits an average relative error percentage of less than 5% compared to traditional fault injection estimation.

This paper presents a technique to improve the reliability and the mean time to failure (MTTF) of hardware task graphs (TGs) running on reconfigurable computers. This technique, which has been named task early fetch, can be applied to a sequence of one or several applications, represented as TGs. It consists in carrying out the reconfiguration of some tasks within the execution of the previous TG, plus increasing the redundancy level of the early fetched tasks. Experimental results on actual TGs show the positive impacts of the proposed technique. Thus, without deteriorating the execution time (makespan), on average, a 114% MTTF improvement is achieved for no-fault-tolerant TGs, and the improvement is more significant when applying to fault-tolerant TGs. Finally, this paper presents a hardware implementation of a manager that applies these techniques at runtime and steers the execution of the running TGs. It demonstrates that, with 0.03% consumption of flip-flops and look-up tables and also 1.22% occupancy of block random access memory available on the Xilinx Virtex Ultra- Scale XCVU095-2FFVA2104E field programmable gate array, the required runtime computations can be carried out in negligible delays.

Nowadays, Industrial Control Systems (ICSs) are employed to monitor and control safety-critical industrial processes. A Supervisory Control and Data Acquisition (SCADA) system is an ICS to perform centralized monitoring and also to control field sites in long-distance communication networks. A SCADA is a distributed system composed of several Remote Terminal Units (RTUs) and a Master Terminal Unit (MTU). RTUs interface with field sensors, local control devices, and field actuators, and the MTU gathers data from RTUs, provides an operator interface to display information, and controls remote sites. RTUs are typically connected to the MTU through a client/server network. Since RTUs operate commonly in a harsh industrial environment, fault tolerance is a key requirement, especially for safety-critical industrial processes. Studies show that a significant number of transient faults caused by a harsh environment lead to control flow errors in the RTU's processors. A control flow checking technique, called PLC-CFC, has been proposed to detect control flow errors in several RTUs in a SCADA system. The proposed technique can be applied to all ICSs which employ microcontrollers, microprocessors, PLCs, or personal computers as their RTUs. The proposed technique has been experimentally evaluated on a real ICS consists of some PLC devices and a main server. For experimental evaluation, 30,000 faults were injected on distributed system and the PLC-CFC technique detected more than 96.76% of the injected faults. The performance and the memory overheads of the technique are about 18.12% and 16.17% on average, respectively.

To tolerate software faults, N-Version Programming (NVP) and N-Modular Redundant (NMR) techniques are widely employed. In these techniques, N modules operate on the same data and send their outputs to a software voter. Since the voter is a single point of failure in the techniques, availability and safety are essential requirements. In this paper a confidence-based software voting technique is proposed. The proposed technique considers weight oscillation and confidence of each module to improve availability and safety of the voter. Evaluation results showed that availability and safety of confidence-based software voter in contrast with standard majority voter and adaptive majority voter has improved about 4.4%, 4.9%, and 5.8% for three error injection scenarios.

FlexRay communication protocol is expected becoming the de-facto standard for distributed safety-critical systems. In this paper, transient single bit-flip faults were injected into the FlexRay communication controller to categorize and analyze the activated faults. In this protocol, an activated fault results in one or more error types which are boundary violation, conflict, content, freeze, synchronization, and syntax. To study the activated faults, a FlexRay bus network, composed of four nodes, was modeled by verilog HDL; and a total of 135,600 transient faults were injected in only one node, where 9,342 (6.9%) of the faults were activated. The results show that the synchronization error is the widespread error with the occurrence ratio of about 70.1%. The Boundary violation and the syntax errors have the occurrence ratios of 32.4% and 24.6%, respectively. The results also show that the Freeze error which more frequent resulted system failures has the occurrence ratio of about 17.3%.

This paper proposes a low-cost fault-tolerant Carry Look-Ahead (CLA) adder which consumes much less power and area overheads in comparison with other fault-tolerant CLA adders. Analytical and experimental results show that this adder corrects all single-bit and multiple-bit transient faults. The Power-Delay Product (PDP) and area overheads of this technique are decreased at least 82% and 71%, respectively, as compared to adders which use traditional TMR, parity prediction, and duplication techniques.