Ensuring power integrity in advanced IC design is increasingly challenging, as excessive IR drop can severely impact circuit performance and reliability, especially during the late-stage Engineering Change Order (ECO) process. In this work, we propose a novel IR drop-aware ECO framework that addresses IR drop violations through targeted cell displacement while minimizing timing and layout disruption. Our approach incorporates vertical IR drop mitigation and horizontal timing fix, and employs a rail severity scoring mechanism that combines current correlation and spatial proximity to evaluate IR drop severity. Experimental results on three post-routed benchmark designs demonstrate that our method achieves significant reductions in worst-case dynamic voltage drop for certain designs and mitigates local timing degradation. Additionally, the proposed severity score accurately reflects trends in IR drop risk, providing valuable guidance for ECO optimization.

Interposer-based packaging has gained tremendous popularity in integrating advanced logic and memory chiplets for artificial intelligence and high-performance computing systems. The size of the silicon interposer is the critical bottleneck in improving the performance of integrated systems by mounting more and more advanced chiplets, such as high bandwidth memory (HBM). Nowadays, ultra large wafer scale integration is a popular alternative to integrate large amounts of advanced chiplets on a big wafer scale silicon interposer. However, wafer scale silicon interposers cannot be manufactured by one mask due to the reticle limitation. Therefore, the mask stitching technique is used to manufacture ultra large systems by applying multiple masks for different sub-regions of an ultra large silicon interposer. To achieve the alignment of two adjacent sub-regions manufactured by different masks, the two sub-regions have an overlapped stitching region. Previous algorithms cannot handle the special design rules of mask stitching regions and are not efficient enough to generate high-quality routing solutions. In this work, we propose a fast routing algorithm for mask stitching regions to efficiently solve the special design rules. The time complexity of the proposed algorithm is O(n log n), where n is the number of nets. Compared with state-of-the-art work, our algorithm can achieve 100% routability with an effective reduction of wirelength. Furthermore, the proposed algorithm can achieve a speedup of thousands of times.

Projection-based model order reduction (MOR) for systems with many input/output (I/O) ports has been a long-standing challenge. While existing techniques offer partial solutions, reducing systems with millions of nodes and tens of thousands of ports remains extremely difficult. Such reductions, however, are important in many modern industrial applications, such as chip power modeling for 3DIC. In this work, we propose a new strategy to address this problem using multi-fidelity machine learning. The process begins with an aggressive port reduction process, followed by a conventional MOR method such as PRIMA. This results in a reduced-order model (ROM) with (much) fewer ports, offering a low-fidelity approximation of the original system. Next, the original full-scale system is simulated in the time domain using representative input waveforms to generate a limited amount of high-fidelity data. This data is used to train a compensation network that learns to bridge the gap between the low-fidelity model output and the true system behavior. To further enhance the efficiency of compensation network training, we devise a tensorized mapping technique that captures the correlations across ports and transient responses, allowing the network to learn more effectively from limited high-fidelity samples. Numerical experiments demonstrate that our approach can solve large-scale MOR problems in a highly cost-effective and scalable manner. It also exhibits a promising level of generalizability in handling input waveforms that differ from the training data.

Exponential integrator (EI) methods have been a promising alternative to backward differentiation formulas (BDF) for transient circuit simulation. However, application of EI to generic nonlinear circuits has achieved only limited success so far, due to numerical instability and difficulty in combining with Newton iterations. In this work, we propose a new nonlinear EI framework, EI-TR, with a novel implicit regularization scheme and a truncated rational (TR) approximation for the treatment of nonlinear functions. The former employs a smart eigenvalue modification to avoid the system partition in the SOTA EI-NK that may induce numerical instability in nonlinear system partitioning. The latter decouples the solutions of the linear and nonlinear systems and reduces the three-layer nested iteration in EI-NK to one single Newton loop similar to conventional BDF, thereby significantly enhancing the performance and robustness of EI for generic nonlinear circuits. Numerical results demonstrate that EI-TR reduces Newton iterations by 3× compared to EI-NK and achieves 6.5x larger time steps than traditional trapezoidal methods.

High-speed serial links are essential for low-latency, high-bandwidth communication in data-intensive systems. Signal integrity (SI) of transmitters (TXs) directly impacts transmission quality of the links, while TXs' delay also introduces timing mismatches that degrade link integrity. In this paper, we propose LiTformer, a Transformer-based model for efficient SI analysis of high-speed link TXs, featuring a non-sequential encoder and a multi-head Transformer decoder to incorporate link parameters and capture long-range dependencies. By adopting a nonautoregressive approach, it enables parallel sequence prediction. We also introduce an ANN-based delay model for fast TX delay estimation. Considering link factors including crosstalk in multiple-link systems, LiTformer enables accurate and fast long-sequence signal prediction at high data rates, achieving efficient SI analysis for TXs. Experimental results show LiTformer achieves 437-996 × speedup in eye diagram prediction over SPICE, with mean errors of 0.15-1.57%. It supports 4-bit signals at Gbps data rates for single-ended and differential TXs, including NRZ and PAM4 formats. The delay model predicts TX delay achieving a speedup of four orders of magnitude with errors of 0.86-2.69%.

Emerging domains, such as artificial intelligence, 5G mobile, and automotive, are increasingly reliant on high-speed circuits for efficient processing, in which achieving high operating frequencies and data rates is crucial to enable productive data exchange and rapid responses. High-speed data as well as low noise margin in the high-speed serial links call for efficient models of drivers. In this article, we propose a fast machine-learning-driven macromodel for high-speed drivers, which can efficiently capture the nonlinear characteristics of drivers considering dynamic supply noise with low model complexity. A decoupling-superposition strategy is employed to effectively calculate the impact of power supply noise. Additionally, we introduce a piecewise-segmented method for macromodel solving to further enhance the speed of model utilization. Experimental results demonstrate that compared to HSPICE, the proposed macromodel achieves up to$50\times $–$1200\times $speedup while maintaining sufficient accuracy, even for signals with GHz data rate.

Superconducting quantum computing hardware relies on classical radio-frequency (RF) electronic circuits to control and measure quantum states. As the complexity of quantum computers increases, the significance of the classical circuitry component grows, necessitating the development of accurate models for its design and optimization. This study presents an analytical model that quantifies the influence of circuit nonidealities on readout fidelity in superconducting quantum computing systems. This model considers a wide range of nonidealities typically encountered in the readout chain, encompassing frequency, amplitude, phase inaccuracies, impedance mismatch, quantum noise, and amplifier noise. It further predicts the combined impact of these nonidealities on fidelity. The model’s precision and efficacy are confirmed through numerical quantum-classical co-simulation. The highest observed relative mismatch is roughly 3.5%, but most errors remain below 1%. Such a model can significantly aid in designing and optimizing practical quantum computers.

High-speed serial links are fundamental to energy-efficient and high-performance computing systems such as artificial intelligence, 5G mobile and automotive, enabling low-latency and high-bandwidth communication. Transmitters (TXs) within these links are key to signal quality, while their modeling presents challenges due to nonlinear behavior and dynamic interactions with links. In this paper, we propose LiTformer: a Transformer-based model for high-speed link TXs, with a non-sequential encoder and a Transformer decoder to incorporate link parameters and capture long-range dependencies of output signals. We employ a non-autoregressive mechanism in model training and inference for parallel prediction of the signal sequence. LiTformer achieves precise TX modeling considering link impacts including crosstalk from multiple links, and provides fast prediction for various long-sequence signals with high data rates. Experimental results show that LiTformer achieves 148--456× speedup for 2-link TXs and 404--944× speedup for 16-link with mean relative errors of 0.68--1.25%, supporting 4-bit signals at Gbps data rates of single-ended and differential TXs, as well as PAM4 TXs.

In this paper, we introduce a parallel-in-time exponential integrator (EI) method, EI-PIT, designed to expedite the transient simulation of linear circuits. By leveraging the linear superposition principle, we decompose the solution at each time point into two components: one resulting from the natural decay of the initial state and the other induced from input excitation. The decay components are processed by computing a single matrix-exponential-vector product over the entire simulation span using the rational Krylov subspace method. Subsequently, the back-scaling technique exploits the scaling invariant property of the Krylov subspace to derive solutions at intermediate time points. The excitation component at any given time point is obtained by approximating a sequence of composite matrix exponential functions, each multiplied by input vectors at varying time points. Given that these inputs are predefined and independent, and the system matrix is constant, the computation-intensive process of generating Krylov subspaces can be performed in parallel. Two enhancement techniques, fast computation of the functions with input slopes based on subspace reuse, and parallelization in batches, are also developed to further boost the performance of EI-PIT.

Quantum computers based on spin qubits and superconducting qubits require radio-frequency (RF) electronic circuits to control and read out the state. As the scale of the quantum processors increases, the inaccuracy in the RF circuit becomes an increasingly significant source of nonidealities that impacts the qubit operations. In this article, we propose a closed-form model to characterize the effects of inaccuracies in the controlling RF circuits on the fidelity of single-qubit control operation of superconducting qubits. Different from previous works, our model allows characterization of multiple inaccuracies at the same time, significantly enhancing the guidance capabilities for practical quantum computing hardware design and optimization. In addition, the accuracy of the proposed model is also verified by a quantum-classical co-simulator.

Model order reduction (MOR) has long been a mainstream strategy to accelerate large scale transient circuit simulation. Exponential integrator (EI) based on Krylov subspace approximation methods, on the other hand, are more recently developed for a similar goal. This article aims to examine in-depth the underlying relationship between model order reduction (MOR) and exponential integrator (EI) that are commonly seen as two separate methods. The main finding is that EI can be viewed as a moment-matching MOR in the time-domain. Specifically, EI, under certain conditions, is equivalent to performing moment-matching MOR based on rational Krylov subspace projection at each time step with a single input vector and a selected expansion point, then advancing the reduced system one step in the time-domain. The equivalence is mathematically proved under different settings and numerically verified in the experiments. Their differences in the transient circuit analysis context are also elaborated from various perspectives. It is hoped that these new insights would benefit the future development of this classical EDA topic.

Periodic small-signal analysis plays an essential role in RF circuit simulation. These analyses encounter substantial computational complexity and memory requirements as the circuit size increases. To address this challenge, iterative solvers combined with the recycling Krylov subspace method between different frequencies have been proposed as a practical approach to speed up small-signal RF analysis. However, existing recycling iterative methods were derived only with the first-order backward Euler (BE) method. In this work, we propose a recycling Krylov subspace iteration method combined with high-order time integration methods to improve the efficiency of small-signal RF analysis. High-order time integration methods help reduce the time points involved in the preceding large-signal analysis and the matrix size of the small-signal equations in periodic small-signal analysis. The recycling Krylov subspace technology further accelerates the solution of these small-signal equations. Numerical experiments confirm the efficacy and advantages of the proposed method for Periodic AC (PAC) and Periodic Noise (PNoise) analysis.

Learning low-bitwidth convolutional neural networks (CNNs) is challenging because performance may drop significantly after quantization. Prior arts often quantize the network weights by carefully tuning hyperparameters such as nonuniform stepsize and layerwise bitwidths, which are complicated since the full- and low-precision representations have large discrepancies. This work presents a novel quantization pipeline, named frequency-aware transformation (FAT), that features important benefits: 1) instead of designing complicated quantizers, FAT learns to transform network weights in the frequency domain to remove redundant information before quantization, making them amenable to training in low bitwidth with simple quantizers; 2) FAT readily embeds CNNs in low bitwidths using standard quantizers without tedious hyperparameter tuning and theoretical analyses show that FAT minimizes the quantization errors in both uniform and nonuniform quantizations; and 3) FAT can be easily plugged into various CNN architectures. Using FAT with a simple uniform/logarithmic quantizer can achieve the state-of-the-art performance in different bitwidths on various model architectures. Consequently, FAT serves to provide a novel frequency-based perspective for model quantization.

Electromigration (EM) has become the major concern for integrated circuits (ICs) in advanced technology nodes. Traditional empirical EM models, such as Black’s equation, show inaccurate estimation for the time-to-failure of ICs, thus resulting in unnecessary over-design. To address this drawback, we propose a few analytical solutions for calculating the transient stress evolution and void volume in straight multisegment interconnect trees during the post-voiding phase. By employing the Laplace transform, the proposed method aims at solving coupled partial differential equations (PDEs) governed by physics-based EM modeling. The analytical solutions can be tailored to expressions with required accuracy and computational savings, leading to a compact end-to-end system providing results of EM failure effects at arbitrary time instances and locations of interconnect trees with varying geometry under time-dependent current and temperature stressing. The EM lifetime such as the incubation time, related to the void volume evolution, at any desired precision, can be calculated by the analytical solutions. The proposed method shows its accuracy, scalability, and computational savings through results compared with the finite element method (FEM) tool COMSOL and the competing methods and can achieve up to$593\times $speedup with < 10% error in EM failure time estimation.

Electromigration (EM) is one of the major concerns in the reliability analysis of very large-scale integration (VLSI) systems due to the continuous technology scaling. Accurately predicting the time-to-failure of integrated circuits (ICs) becomes increasingly important for modern IC design. However, traditional methods are often not sufficiently accurate, leading to undesirable over-design especially in advanced technology nodes. In this article, we propose an approach using multilayer perceptrons (MLPs) to compute stress evolution in the interconnect trees during the void nucleation phase. The availability of a customized trial function for neural network training holds the promise of finding dynamic mesh-free stress evolution on complex interconnect trees under time-varying temperatures. Specifically, we formulate a new objective function considering the EM-induced coupled partial differential equations (PDEs), boundary conditions (BCs), and initial conditions to enforce the physics-based constraints in the spatial–temporal domain. The proposed model avoids meshing and reduces temporal iterations compared with conventional numerical approaches like finite element method. Numerical results confirm its advantages on accuracy and computational performance.

Being a promising candidate for future nonvolatile memory and neuromorphic computing, spin-transfer-torque magnetic tunnel junction (STT-MTJ) devices are gaining substantial momentum in industrial adoption in recent years, calling for EDA support for higher modeling capabilities. However, the complex interplay of multiple physical mechanisms featured in MTJ devices imposes substantial challenges to their numerical modeling. In this work, we propose a fully coupled, transient electronic–magnetic–thermal (TEMT) modeling approach for STT-MTJ devices. Aiming to be the first principle and physically holistic, TEMT combines the atomistic nonequilibrium Green’s function (NEGF) model for tunneling currents, the Landau–Lifshitz–Gilbert–Slonczewski (LLGS) equation for magnetic dynamics and the heat conduction equation (HCE) for thermal dynamics in a self-consistent manner. To alleviate computational burden, we also devise an analytical approximation approach to reduce the number of NEGF solutions in the TEMT framework, which leads to over$15\times $speedup with a very mild accuracy loss. An in-depth investigation of STT-MTJ devices using the TEMT framework is conducted to demonstrate its benefits and performance.

Exponential integrator (EI) method has been proved to be an effective technique to accelerate large-scale transient power/ground network analysis. However, EI requires the inputs to be piece-wise linear (PWL) in one step, which greatly limits the step size when the inputs are poorly aligned. To address this issue, in this work we first elucidate with mathematical proof that EI, when used together with the rational Krylov subspace, is equivalent to performing a moment-matching model order reduction (MOR) with single input in each time step, then advancing the reduced system using EI in the same step. Based on this equivalence, we next devise a hybrid method, EI-MOR, to combine the usage of EI and MOR in the same transient simulation. A majority group of well-aligned inputs are still treated by EI as usual, while a few misaligned inputs are selected to be handled by a MOR process producing a reduced model that works for arbitrary inputs. Therefore the step size limitation imposed by the misaligned inputs can be largely alleviated. Numerical experiments are conducted to demonstrate the efficacy of the proposed method.

In this article, we propose an exponential-integrator-Newton–Krylov (EI-NK) method for transient simulation of large-scale nonlinear circuits. This method aims to address two long-standing problems that affect the performance and robustness of EI in handling nonlinear circuits. First is the numerical instability caused by the singularity in the differential-algebraic equation system. We provide an in-depth analysis of the problem and propose a systematic, algebraic, and sparsity preserving regularization technique to eliminate the unstable modes in the system to be solved. Next, we develop a scheme to enable the iterative Newton–Raphson solution in the EI framework for enhanced nonlinearity handling capability. With the two techniques, we wish to elevate EI’s robustness and performance and make it a competitive alternative to the existing SPICE-type simulators in practical applications.

The electromigration (EM)-induced reliability issues in very large-scale integration (VLSI) circuits have attracted increased attention due to the continuous technology scaling. Traditional EM models often lead to overly pessimistic predictions incompatible with the shrinking design margin in future technology nodes. Motivated by the latest success of neural networks in solving differential equations in physical problems, we propose a novel mesh-free model to compute EM-induced stress evolution in VLSI circuits. The model utilizes a specifically crafted space–time physics-informed neural network (STPINN) as the solver for EM analysis. By coupling the physics-based EM analysis with dynamic temperature incorporating Joule heating and via effect, we can observe stress evolution along multisegment interconnect trees under constant, time-dependent, and space–time-dependent temperature during the void nucleation phase. The proposed STPINN method obviates the time discretization and meshing required in conventional numerical stress evolution analysis and offers significant computational savings. Numerical comparison with competing schemes demonstrates a$2\times $–$52\times $speedup with a satisfactory accuracy.

In this paper, we aim to address two long-lasting issues in large scale transient circuit simulation using the exponential integrator (EI) method. First is the numerical instability caused by the singularity in the differential-algebraic equation system. Our proposed solution is a systematic, algebraic and sparsity preserving regularization technique to eliminate the unstable modes in the system to be solved. Next, we devise a generic scheme to apply Newton-Raphson iterations in the EI framework for enhanced nonlinearity handling capability. With the two techniques, we wish to elevate the robustness and performance of EI and make it a competitive alternative to the existing SPICE-type simulators in practical usage.

This paper presents a new transient electro-thermal (ET) simulation method for fast 3D chip-level analysis of power electronics with field solver accuracy. The metallization stacks are meshed and solved with 3D field solver using nonlinear temperature-dependent parameters, and the active devices are modeled with nonlinear tabular compact models to avoid time-consuming TCAD simulation. The main contributions include: 1) A tightly-coupled formulation that solves the electrical and thermal systems simultaneously to enable a more natural characterization of ET interaction and faster convergence for strong ET coupling; 2) A specialized exponential-integrator-Newton-Krylov (EI-NK) transient solver to address the numerical challenges arising from the tightly-coupled ET simulation. Numerical experiments show that the proposed method out-performs the existing implicit time stepping with the Newton's method and the exponential integrator with an explicit nonlinear approximation.

This paper presents a new transient electro-thermal simulation method for fast 3-D chip-level analysis of power electronics with field solver accuracy. The metallization stack and substrate are meshed and solved with 3-D field solver using nonlinear temperature-dependent electrical and thermal parameters, and the active transistors are modeled with table models to avoid time-consuming technology computer-aided design simulation. Two contributions are made to enhance the physical relevance and the computational performance: 1) the capacitive effects, including interconnect parasitic capacitance and gate capacitance of power devices with nonlinear dependence on bias and temperature, are explicitly accounted for and 2) a specialized nonlinear exponential integrator (EI) method is developed to address the considerably different time scales between electrical and thermal sectors. The EI-based transient solver allows the electrical system to step with much larger time steps than in conventional methods, thus the time step gap between the electrical and the thermal simulation is largely reduced.

Matrix exponential (MEXP) method has been demonstrated to be a competitive candidate for transient simulation of very large-scale integrated circuits. Nevertheless, the performance of MEXP based on ordinary Krylov subspace is unsatisfactory for stiff circuits, wherein the underlying Arnoldi process tends to oversample the high magnitude part of the system spectrum while undersampling the low magnitude part that is important to the final accuracy. In this work we explore the use of extended Krylov subspace to generate more accurate and efficient approximation for MEXP. We also develop a formulation that allows unequal positive and negative dimensions in the generated Krylov subspace for better performance. Numerical results demonstrate the efficacy of the proposed method.

We report recent progress in developing a numerically efficient formulation for electromagnetic-technology computer-aided design cosimulation for fast-transient computations. The difficulties underlying the currently existing transient formulation stemming from the vector potential-scalar potential (A-V) framework are analyzed. A time-domain electric field-scalar potential (E-V) framework is then developed via equation and variable transformations. This results in better-conditioned systems that are friendly to iterative solutions at fast switching times. Numerical examples show that the proposed E-V solver renders a useful tool for addressing multidomain simulation.

In this paper, we present a variational electromagnetic-semiconductor coupled solver to assess the impacts of process variations on the 3D integrated circuit (3D IC) on-chip structures. The solver employs the finite volume method (FVM) to handle a system of equation considering both the full-wave electromagnetic effects and semiconductor effects. With a smart geometrical variation model for the FVM discretization, the solver is able to handle both small-size or large-size variations. Moreover, a weighted principle factor analysis (wPFA) technique is presented to reduce the random variables in both electromagnetic and semiconductor regions, and the spectral stochastic collocation method (SSCM) is used to generate the quadratic statistical model. Numerical results validate the accuracy and efficiency of this solver in dealing with process variations in hybrid material through-silicon via (TSV) structures.

We present a fast time-domain multiphysics simulation framework that combines full-wave electromagnetism (EM) and carrier transport in semiconductor devices (TCAD). The proposed framework features a division of linear and nonlinear components in the EM-TCAD coupled system. The former is extracted and handled independently with high efficiency by a matrix exponential approach assisted with Krylov subspace method. The latter is treated by ordinary Newton's method yet with a much sparser Jacobian matrix that leads to substantial speedup in solving the linear system of equations. More convenient error management and adaptive control are also available through the linear and nonlinear decoupling.

We propose an advanced matrix exponential method (MEXP) to handle the transient simulation of stiff circuits and enable parallel simulation. We analyze the rapid decaying of fast transition elements in Krylov subspace approximation of matrix exponential and leverage such scaling effect to leap larger steps in the later stage of time marching. Moreover, matrix-vector multiplication and restarting scheme in our method provide better scalability and parallelizability than implicit methods. The performance of ordinary MEXP can be improved up to 4.8 times for stiff cases, and the parallel implementation leads to another 11 times speedup. Our approach is demonstrated to be a viable tool for ultra-large circuit simulations (with 1.6M ~ 12M nodes) that are not feasible with existing implicit methods.

Fast full-chip time-domain simulation calls for advanced numerical integration techniques with capability to handle the systems with (tens of) millions of variables resulting from the modified nodal analysis (MNA). General MNA formulation, however, leads to a differential algebraic equation (DAE) system with singular coefficient matrix, for which most of explicit methods, which usually offer better scalability than implicit methods, are not readily available. In this paper, we develop a practical two-stage strategy to remove the singularity in MNA equations of large-scale circuit networks. A topological index reduction is first applied to reduce the DAE index of the MNA equation to one. The index-1 system is then fed into a systematic process to eliminate excess variables in one run, which leads to a nonsingular system. The whole regularization process is devised with emphasis on exact equivalence, low complexity, and sparsity preservation, and is thus well suited to handle extremely large circuits.

We propose an explicit numerical integration method based on matrix exponential operator for transient analysis of large-scale circuits. Solving the differential equation analytically, the limiting factor of maximum time step changes largely from the stability and Taylor truncation error to the error in computing the matrix exponential operator. We utilize Krylov subspace projection to reduce the computation complexity of matrix exponential operator. We also devise a prediction-correction scheme tailored for the matrix exponential approach to dynamically adjust the step size and the order of Krylov subspace approximation. Numerical experiments show the advantages of the proposed method compared with the implicit trapezoidal method.

In circuit simulation, when a large RLC network is connected with delay elements, such as transmission lines, the resulting system is a time-delay system (TDS). This paper presents a new model order reduction (MOR) scheme for TDSs with state time delays. It is the first time to reduce a TDS using balanced truncation. The Lyapunov-type equations for TDSs are derived, and an analysis of their computational complexity is presented. To reduce the computational cost, we approximate the controllability and observability Gramians in the frequency domain. The reduced-order models (ROMs) are then obtained by balancing and truncating the approximate Gramians. Numerical examples are presented to verify the accuracy and efficiency of the proposed algorithm.

We develop a new method based on the high-frequency electromagnetic (EM)-semiconductor coupled simulation to analyze the impact of multi-type process variations happen around semiconductor-metal structure. It is competent to simultaneously handle geometrical variations like surface roughness and material variations like semi-conductor doping profile, which are difficult for traditional "stand alone" simulation methods. A sparse grid based stochastic spectral collocation method (SSCM) combined with principle factor analysis (PFA) is implemented to accelerate the stochastic simulation. Numerical results confirm the validity and significance of our variational coupled simulation framework.

This paper presents an effective formulation tailored for electromagnetic-technology computer-aided design coupled simulations for extremely-high-frequency ranges and beyond (>;50 GHz). A transformation of variables is exploited from the starting A-V formulation to the E-V formulation, combined with adopting the gauge condition as the equation for scalar potential. The transformation significantly reduces the cross-coupling between electric and magnetic systems at high frequencies, providing therefore much better convergence for iterative solution. The validation of such transformations is ensured through a careful analysis of redundancy in the coupled system and material properties. Employment of the advanced matrix permutation technique further alleviates the extra computational cost introduced by the variable transformation. Numerical experiments confirm the accuracy and efficiency of the proposed E-V formulation.

As clock frequencies exceed giga-Hertz, the extra power loss due to conductor surface roughness in interconnects and packagings is more evident and thus demands a proper accounting for accurate prediction of signal integrity and energy consumption. Existing techniques based on analytical approximation often suffer from a narrow valid range, i.e., small or large limit of roughness. In this paper, we propose a new simulation methodology for surface roughness loss that is applicable to general surface roughness and a wide frequency range. The method is based on 3D statistical modeling of surface roughness and the numerical solution of scalar wave modeling (SWM) with the method of moments (MOM). The spectral stochastic collocation method (SSCM) is applied in association of random surface modeling to avoid the time-consuming Monte-Carlo (MC) simulation. Comparisons with existing methods in their respective valid region then verify the effectiveness of our approach.

In multigigahertz integrated-circuit design, the extra energy loss caused by conductor surface roughness in metallic interconnects and packagings is more evident than ever before and demands explicit consideration for accurate prediction of signal integrity and energy consumption. Existing techniques based on analytical approximation, despite simple formulations, suffer from restrictive valid ranges, namely, either small or large roughness/frequencies. In this paper, we propose a robust and efficient numerical-simulation methodology applicable to evaluating general surface roughness, described by parameterized stochastic processes, across a wide frequency band. Traditional computation-intensive electromagnetic simulation is avoided via a tailored scalar-wave modeling to capture the power loss due to surface roughness. The spectral stochastic collocation method is applied to construct the complete statistical model. Comparisons with full wave simulation as well as existing methods in their respective valid ranges then verify the effectiveness of the proposed approach.

This paper proposes an efficient model for numerically evaluating the impact of random surface roughness on the internal impedance for large-scale interconnect structures. The effective resistivity (ER) and effective permeability (EP) are numerically formulated to avoid the computationally prohibitive global discretization, while maintaining the model accuracy and flexibility. A modified stochastic integral equation (SIE) method is proposed to significantly speed up the computation for the mean values of ER and EP under the assumption of random surface roughness. Numerical experiments then verify the efficacy of our approach.