Binary neural network (BNN) delivers increased compute intensity and reduces memory/data requirements for computation. Scalable BNN enables inference in a limited time due to different constraints. This paper explores the application of Scalable BNN in oblivious inference, a service provided by a server to mistrusting clients. Using this service, a client can obtain the inference result on his/her data by a trained model held by the server without disclosing the data or learning the model parameters. Two contributions of this paper are: (1) we devise lightweight cryptographic protocols explicitly designed to exploit the unique characteristics of BNNs. (2) we present an advanced dynamic exploration of the runtime-accuracy tradeoff of scalable BNNs in a single-shot training process. While previous works trained multiple BNNs with different computational complexities (which is cumbersome due to the slow convergence of BNNs), we train a single BNN that can perform inference under various computational budgets. Compared to CryptFlow2, the state-of-the-art technique in the oblivious inference of non-binary DNNs, our approach reaches 3× faster inference while keeping the same accuracy. Compared to XONN, the state-of-the-art technique in the oblivious inference of binary networks, we achieve 2× to 12× faster inference while obtaining higher accuracy.

Manipulated media is becoming a prominent threat due to the recent advances in realistic image and video synthesis techniques. There have been several attempts at detecting synthetically tampered media using machine learning classifiers. However, such classifiers do not generalize well to black-box image synthesis techniques and have been shown to be vulnerable to adversarial examples. To address these challenges, we introduce FaceSigns —a deep learning-based semi-fragile watermarking technique that allows media authentication by verifying an invisible secret message embedded in the image pixels. Instead of identifying and detecting manipulated media using visual artifacts, we propose to proactively embed a semi-fragile watermark into a real image or video so that we can prove its authenticity when needed. FaceSigns is designed to be fragile to malicious manipulations or tampering while being robust to benign operations such as image/video compression, scaling, saturation, contrast adjustments, and so forth. This allows images and videos shared over the internet to retain the verifiable watermark as long as a malicious modification technique is not applied. We demonstrate that our framework can embed a 128-bit secret as an imperceptible image watermark that can be recovered with a high bit recovery accuracy at several compression levels, while being non-recoverable when unseen malicious manipulations are applied. For a set of unseen benign and malicious manipulations studied in our work, our framework can reliably detect manipulated content with an AUC score of 0.996, which is significantly higher than prior image watermarking and steganography techniques.

Privacy-preserving federated learning allows multiple users to jointly train a model with coordination of a central server. The server only learns the final aggregation result, thereby preventing leakage of the users’ (private) training data from the individual model updates. However, keeping the individual updates private allows malicious users to degrade the model accuracy without being detected, also known as Byzantine attacks. Best existing defenses against Byzantine workers rely on robust rank-based statistics, e.g., setting robust bounds via the median of updates, to find malicious updates. However, implementing privacy-preserving rank-based statistics, especially median-based, is nontrivial and unscalable in the secure domain, as it requires sorting of all individual updates. We establish the first private robustness check that uses high break point rank-based statistics on aggregated model updates. By exploiting randomized clustering, we significantly improve the scalability of our defense without compromising privacy. We leverage the derived statistical bounds in zero-knowledge proofs to detect and remove malicious updates without revealing the private user updates. Our novel framework, zPROBE, enables Byzantine resilient and secure federated learning. We show the effectiveness of zPROBE on several computer vision benchmarks. Empirical evaluations demonstrate that zPROBE provides a low overhead solution to defend against state-of-the-art Byzantine attacks while preserving privacy.

This paper proposes AdaTest, a novel adaptive test pattern generation framework for efficient and reliable Hardware Trojan (HT) detection. HT is a backdoor attack that tampers with the design of victim integrated circuits (ICs) . AdaTest improves the existing HT detection techniques in terms of scalability and accuracy of detecting smaller Trojans in the presence of noise and variations. To achieve high trigger coverage, AdaTest leverages Reinforcement Learning (RL) to produce a diverse set of test inputs. Particularly, we progressively generate test vectors with high ‘reward’ values in an iterative manner. In each iteration, the test set is evaluated and adaptively expanded as needed. Furthermore, AdaTest integrates adaptive sampling to prioritize test samples that provide more information for HT detection, thus reducing the number of samples while improving the samples’ quality for faster exploration. We develop AdaTest with a Software/Hardware co-design principle and provide an optimized on-chip architecture solution. AdaTest’s architecture minimizes the hardware overhead in two ways: (i) Deploying circuit emulation on programmable hardware to accelerate reward evaluation of the test input; (ii) Pipelining each computation stage in AdaTest by automatically constructing auxiliary circuit for test input generation, reward evaluation, and adaptive sampling. We evaluate AdaTest’s performance on various HT benchmarks and compare it with two prior works that use logic testing for HT detection. Experimental results show that AdaTest engenders up to two orders of test generation speedup and two orders of test set size reduction compared to the prior works while achieving the same level or higher Trojan detection rate.

Timing errors of microelectronic circuits occur when the circuit timing specification is violated, i.e., the dynamic delay of circuits exceeds the circuit clock period. With the continuous scaling of CMOS technology, microelectronic circuits are increasingly susceptible to microelectronic variations such as variations in operating conditions. Such variations can cause delay uncertainty in microelectronic circuits, leading totiming errors. Circuit designers typically combat these errors using conservative guardbands in the circuit and architectural design, which can, however, cause significant loss of operational efficiency. In this article, we proposeDEVoT, a supervised learning model that can predict the dynamic delay of functional units (FUs) under different operating conditions, clock speeds, and input workload. The main contribution ofDEVoTis to jointly consider the impact of voltage, temperature, and input workload in path sensitization, hence predicting the dynamic delay. We measure the dynamic delay using switching activity generated through gate-level simulation of post place-and-route design in the TSMC 45-nm process. We characterize the delay of FUs under different operating conditions and input workload. We then extract useful features in the input workload that influences dynamic path sensitization. Using these features, we apply supervised learning methods to buildDEVoT. Across 100 different operating conditions, four widely used FUs, and three datasets,DEVoTachieves, on average, less than 2% relative deviation from the ground truth and is$100\times $faster than the gate-level simulation. We present two case studies usingDEVoT. First, we useDEVoTto predict timing errors of FUs, andDEVoTachieves an average prediction accuracy at 98.04%. We further useDEVoTto estimate application output quality under different operating conditions, andDEVoTachieves an average estimation accuracy at 97% for two image processing applications. Second, we present a fuzzing-based method to identify “critical” patterns that can cause longer delay for a given circuit. Built on top ofDEVoT, the generated input patterns can improve the sensitized delay by up to 8.3% compared to random patterns.DEVoTalso outperforms automatic test pattern generation (ATPG) in sensitizing circuit delay. We will opensourceDEVoT, which can assist circuit designers to perform early design space exploration and can also help software developers in approximate computing community to assess their program resilience to hardware approximation without performing circuit simulation.

This study aims to leverage the advances of connected automated vehicle (CAV) technology to design an eco-driving and platooning system that can improve both fuel and operational efficiency of vehicles on the freeways. The proposed algorithm optimizes CAVs’ trajectories with three objectives, including travel time minimization, fuel consumption minimization, and traffic safety improvement, following a two-stage control logic. The first stage, designed for CAV trajectory planning, is carried out with two optimization models. The first model functions to predict the freeway traffic states in the near future and accordingly optimize CAVs’ desired speed profile to minimize total freeway travel time. Notably, the interactions between CAVs and human-driven vehicles (HVs) are described in the embedded traffic flow model and the optimization can fully account for CAVs’ impact to HVs’ speeds. Then grounded on the obtained speed profile, the second eco-driving model would further update it so as to platoon CAVs and minimize their fuel consumption. The second stage, for real-time control purpose, is developed to ensure the operational safety of CAVs. Particularly, based on the speed profile from the first stage, real-time adaptions would be placed on CAVs to dynamically adjust speeds, in response to local driving conditions. To evaluate the proposed algorithms, this study selects a freeway segment of I-15 in Salt Lake City as the study site. The extensive numerical simulation results confirmed the effectiveness of the proposed framework in both mitigating freeway congestion and reducing vehicles’ fuel consumption.

Design hotspots, a.k.a. layout weak points are layout patterns that are susceptible to systematic failure and yield loss in high-volume manufacturing (HVM). Therefore, understanding the yield impact of layout weak point is a crucial step for yield learning. Layout weak points can be identified by layout analysis based on simulation or silicon learning from past failures. In advanced technology nodes, the interaction between design and manufacturing process is increasingly significant, making it paramount to quantify which layout weak points are causing yield loss for a specific manufacturing process. This can be achieved by collecting volume scan diagnosis results and then map the call-outs to suspected weak points for defect root-cause analysis. One major challenge in this process is the often-false assumptions that correlation is causation, especially as scan diagnosis resolution is typically not ideal and random correlation hits can be common as the weak point count grows. In this work, we propose a novel approach for quantitatively assessing the impact of layout weak points on IC failure using statistical methods. We develop a new weak point effectiveness metric to help guide the decision on whether a specific weak point is a root cause in a population of volume scan diagnosis results. Experimental results show that our approach is able to interpret high count weak points for “meaningful” root-cause and rank the relative contribution of different weak point sets.

To improve a vehicle's fuel efficiency when operating on roadways, this study develops an ecological driving system under the connected and automated vehicle (CAV) environment. The system includes three critical functions, including traffic state prediction, eco-driving speed control, and powertrain control implementation. According to the real-time traffic information obtained from vehicle-to-infrastructure and vehicle-to-vehicle communications, the embedded traffic state prediction model will estimate and predict the average speeds and densities of freeway subsections. With an objective of minimizing the fuel consumption, the eco-driving speed control function follows a two-stage hierarchical framework. The first stage, which is executed at the global level, aims to optimize the travel speed profile of the CAV over a certain time period. The second stage, local speed adaption, is designed to dynamically adjust the CAV's speed and make lane-changing decisions based on the local driving condition. The resulting control parameters will then be forwarded to the powertrain control system for implementations. To evaluate the proposed system, this study performs comprehensive numerical tests by using simulation models. This results confirm the effectiveness of the proposed system in reducing fuel consumption. Further comparisons with different models highlights the need to consider traffic state information in the first-stage optimization and lane-changing decision module in the local adaption function.

Yield estimation is an indispensable piece of information at the onset of high-volume production of a device, as it can inform timely process and design refinements in order to achieve high yield, rapid ramp-up, and fast time-to-market. To date, yield estimation is generally performed through simulation-based methods. However, such methods are not only very time-consuming for certain circuit classes, but also limited by the accuracy of the statistical models provided in the process design kits (PDKs). In contrast, herein we introduce yield estimation solutions which rely exclusively on silicon measurements and we apply them toward predicting yield during: 1) production migration from one fabrication facility to another and 2) transition from one design generation to the next. These solutions are applicable to any circuit, regardless of PDK accuracy and transistor-level simulation complexity, and range from rather straightforward to more sophisticated ones, capable of leveraging additional sources of silicon data. Effectiveness of the proposed yield forecasting methods is evaluated using actual high-volume production data from two 65-nm RF transceiver devices.

High-cost specification tests of analog/RF devices have become a bottle-neck in reducing the overall cost of high-volume manufacturing (HVM) of systems on chip (SoCs) due to lengthy testing time and expensive test equipment. Especially for fabless semiconductor companies, test time reduction (TTR) is becoming an important priority for developing cost-effective design and manufacturing flow of SoCs. Toward this end, numerous approaches have been developed. In this paper, we point out an important practical issue in implementing feature-selection-based low-cost analog/RF test scheme: in HVM, similar specification tests are often bundled as test suites, which are tested as a whole function by automatic test equipment. Removing some tests in one test suite does not provide much saving on device testing time. We then propose a test-suite-based analog/RF TTR approach using canonical correlation, which aims at identifying correlations between two multivariate sets. We further enhance the incurred test escape by applying a data-driven defect-oriented approach. Experimental results in high-volume industrial data confirm the superiority of the proposed approach over existing methods in terms of both TTR and defective parts per million level.

We introduce a Concurrent Hardware Trojan Detection (CHTD) methodology for wireless cryptographic integrated circuits (ICs), based on continuous extraction of a side-channel fingerprint and evaluation by a trained on-chip neural classifier. While similar statistical side-channel fingerprinting methods have been extensively studied in the past, they operate either before an IC is deployed or, periodically, during idle times, after an IC is deployed. Therefore, they can be easily evaded by a hardware Trojan which remains dormant at all times except during normal operation. In contrast, the proposed methodology operates concurrently with the normal functionality of the IC and is, therefore, much harder to evade. The proposed methodology is demonstrated using a hybrid experimentation platform consisting of (i) a custom-designed wireless cryptographic IC, infested with hardware Trojans that are controllable to be either active or dormant, (ii) a Spice-level simulation model of the fingerprint extraction circuit, and (iii) a custom-designed programmable analog neural network IC. Experimental results corroborate that the proposed CHTD methodology effectively identifies hardware Trojans when they are active, while not incurring any false positives when they are absent or dormant.

Growing demand for more powerful yet smaller devices has resulted in continuous scaling of fabrication technologies. While this approach supports aggressive design specifications, it has resulted in tighter constraints for circuit designers who face yield losses in analog/RF ICs due to process variation. Over the last few years, several statistical techniques have, therefore, been proposed to counter these losses and to recover yield through individual post-manufacturing calibration of each fabricated chip using tuning knobs. These techniques can be broadly classified as iterative or one-shot calibration methods, with the latter having the benefit of being faster and, therefore, more likely to be cost-effective in a high volume manufacturing (HVM) environment. In this paper, we first put three previously proposed one-shot statistical calibration methods to the test using a custom-designed tunable LNA, which was fabricated in IBM's 130nm RF CMOS process. We, then, introduce an improvement to the tuning knob selection criterion, which applies to all three methods, increasing their effectiveness. Finally, we demonstrate the efficacy of a previously proposed approach which uses simulation data and Bayesian model fusion in order to reduce the number of chips required for training the statistical models employed by the three one-shot calibration methods.

We investigate the utility of correlations between e-test and probe test measurements in predicting yield. Specifically, we first examine whether statistical methods can accurately predict parametric probe test yield as a function of e-test measurements within the same fab. Then, we investigate whether the e-test profile of a destination fab, in conjunction with the e-test and probe test profiles of a source fab, suffice for accurate yield prognosis during fab-to-fab product migration. Results using an industrial dataset of ~3.5M devices from a 65nm Texas Instruments RF transceiver design fabricated in two different fabs reveal that (i) within-fab yield prediction error is in the range of a few tenths of a percentile point, and (ii) fab-to-fab yield prediction error is in the range of half a percentile point.

We introduce two statistical methods for identifying recycled integrated circuits (ICs) through the use of one-class classifiers and degradation curve sensitivity analysis. Both methods rely on statistically learning the parametric behavior of known new devices and using it as a reference point to determine whether a device under authentication has previously been used. The proposed methods are evaluated using actual measurements and simulation data from digital and analog devices, with experimental results confirming their effectiveness in distinguishing between new and aged ICs and their superiority over previously proposed methods.

Statistical side channel fingerprinting is a popular hardware Trojan detection method, wherein a parametric signature of a chip is collected and compared to a trusted region in a multi-dimensional space. This trusted region is statistically established so that, despite the uncertainty incurred by process variations, the fingerprint of Trojan-free chips is expected to fall within this region while the fingerprint of Trojan-infested chips is expected to fall outside. Learning this trusted region, however, assumes availability of a small set of trusted (i.e. "golden") chips. Herein, we rescind this assumption and we demonstrate that an almost equally effective trusted region can be learned through a combination of a trusted simulation model, measurements from process control monitors (PCMs) which are typically present either on die or on wafer kerf, and advanced statistical tail modeling techniques. Effectiveness of this method is evaluated using silicon measurements from two hardware Trojan-infested versions of a wireless cryptographic integrated circuit.

Wafer-level spatial correlation modeling of probetest measurements has been explored in the past as an avenue to test cost and test time reduction. In this work, we first improve the accuracy of a popular Gaussian process-based wafer-level spatial correlation method through two key enhancements: (i) confidence estimation-based progressive sampling, and, (ii) inclusion of spatio-temporal features for inter-wafer trend learning. We then explore a new application of the enhanced correlation modeling method in estimating High Volume Manufacturing (HVM) yield from a small set of early wafers and we demonstrate its effectiveness on a large set of actual industrial test data.

Laser trimming is used extensively to ensure accurate values of on-chip precision resistors in the presence of process variations. Such laser resistor trimming is slow and expensive, typically performed in a closed-loop, where the laser is iteratively fired and some circuit parameter (i.e. current) is monitored until a target condition is satisfied. Toward reducing this cost, we introduce a novel methodology for predicting the laser trim length, thereby eliminating the closed-loop control and speeding up the process. Predictions are obtained from waferlevel spatial correlation models, learned from a sparse sample of die on which traditional trimming is performed. Effectiveness is demonstrated on an actual wafer of laser-trimmed ICs.

Achieving automotive quality requires IC tests that achieve 100% coverage of potential defects. With new cell-aware digital test pattern generation techniques and the simple stuck-at fault model, this has proven practical for digital circuitry, but there is no equivalent for mixed-signal circuitry. A simple but realistic analog defect model is described, based on industrial observations and theory. It is consistent with previous proposals, but has novel differences that make it suitable for schematic and layout-extracted netlists and more efficient to simulate. A couple of examples show its effectiveness.

As the electronic component supply chain grows more complex due to globalization, with parts coming from a diverse set of suppliers, counterfeit electronics have become a major challenge that calls for immediate solutions. Currently, there are a few standards and programs available that address the testing for such counterfeit parts. However, not enough research has yet addressed the detection and avoidance of all counterfeit parts-recycled, remarked, overproduced, cloned, out-of-spec/defective, and forged documentation-currently infiltrating the electronic component supply chain. Even if they work initially, all these parts may have reduced lifetime and pose reliability risks. In this tutorial, we will provide a review of some of the existing counterfeit detection and avoidance methods. We will also discuss the challenges ahead for implementing these methods, as well as the development of new detection and avoidance mechanisms.

In an effort to reduce the cost of specification testing in analog/RF circuits, spatial correlation modeling of wafer-level measurements has recently attracted increased attention. Existing approaches for capturing and leveraging such correlation, however, rely on the assumption that spatial variation is smooth and continuous. This, in turn, limits the effectiveness of these methods on actual production data, which often exhibits localized spatial discontinuous effects. In this work, we propose a novel approach which enables spatial correlation modeling of wafer-level analog/RF tests to handle such effects and, thereby, to drastically reduce prediction error for measurements exhibiting discontinuous spatial patterns. The core of the proposed approach is a k-means algorithm which partitions a wafer into k clusters, as caused by discontinuous effects. Individual correlation models are then constructed within each cluster, revoking the assumption that spatial patterns should be smooth and continuous across the entire wafer. Effectiveness of the proposed approach is evaluated on industrial probe test data from more than 3,400 wafers, revealing significant error reduction over existing approaches.

Statistical intra-die correlation has been extensively studied as a means for reducing test cost in analog/RF ICs. Generally known as alternate test, this approach seeks to predict the performances of an analog/RF chip based on low-cost measurements on the same chip and statistical models learned from a training set of chips. Recently, an orthogonal direction for leveraging statistical correlation towards reducing test cost of analog/RF ICs has also gained traction. Specifically, inter-die spatial correlation models learned from specification tests on a sparse subset of die on a wafer are used to predict performances on the unobserved die. In this work, we investigate the potential of combining these two statistical approaches, anticipating that the performance prediction accuracy of the joint correlation model will surpass the accuracy of its constituents. Experimental results on industrial semiconductor manufacturing data validate this conjecture and corroborate the utility of the combined performance prediction models.

Many of the design companies cannot afford owning and acquiring expensive foundries and hence, go fabless and outsource their design fabrication to foundries that are potentially untrustwrothy. This globalization of Integrated Circuit (IC) design flow has introduced security vulnerabilities. If a design is fabricated in a foundry that is outside the direct control of the (fabless) design house, reverse engineering, malicious circuit modification, and Intellectual Property (IP) piracy are possible. In this tutorial, we elaborate on these and similar hardware security threats by making connections to VLSI testing. We cover design-for-trust techniques, such as logic encryption, aging acceleration attacks, and statistical methods that help identify Trojan'ed and counterfeit ICs.

As the supply chain of electronic circuits grows more complex, with parts coming from different suppliers scattered across the globe, counterfeit integrated circuits (ICs) are becoming a serious challenge which calls for immediate solutions. Counterfeiting includes re-labeling legitimate chips or illegitimately replicating chips and deceptively selling them as made by the legitimate manufacturer, or simply selling fake chips. Counterfeiting also includes providing defective parts or simply previously used parts recycled from scrapped assemblies. Obviously, there is a multitude of legal and financial implications involved in such activities and even if these devices initially work, they may have reduced lifetime and may pose reliability risks. In this tutorial, we provide a comprehensive review of existing techniques which seek to prevent and/or detect counterfeit integrated circuits. Various approaches are discussed and an advanced machine learning-based method employing parametric measurements is described in detail.

Monitoring the semiconductor manufacturing process and understanding the various sources of variation and their repercussions is a crucial capability. Indeed, identifying the root-cause of device failures, enhancing yield of future production through improvement of the manufacturing environment, and providing feedback to the designer toward development of design techniques that minimize failure rate rely on such a capability. To this end, we introduce a spatial decomposition method for breaking down the variation of a wafer to its spatial constituents, based on a small number of measurements sampled across the wafer. We demonstrate that by leveraging domain-specific knowledge and by using as constituents dynamically learned, interpretable basis functions, the ability of the proposed method to accurately identify the sources of variation is drastically improved, as compared to existing approaches. We then illustrate the utility of the proposed spatial variation decomposition method in (i) identifying the main contributor to yield variation, (ii) predicting the actual yield of a wafer, and (iii) clustering wafers for production planning and abnormal wafer identification purposes. Results are reported on industrial data from high-volume manufacturing, confirming the ability of the proposed method to provide great insight regarding the sources of variation in the semiconductor manufacturing process.

Fault diagnosis of Integrated Circuits (ICs) has grown into a special field of interest in the Semiconductor Industry. Fault diagnosis is very useful at the design stage for debugging purposes, at high-volume manufacturing for obtaining feedback about the underlying fault mechanisms and improving the design and layout in future IC generations, and in cases where the IC is part of a larger safety-critical system (e.g. automotive, aerospace) for identifying the root-cause of failure and for applying corrective actions that will prevent failure reoccurrence and, thereby, will expand the safety features. In this summary paper, we present a methodology for fault modeling and fault diagnosis of analog circuits based on machine learning. A defect filter is used to recognize the type of fault (parametric or catastrophic), inverse regression functions are used to locate and predict the values of parametric faults, and multi-class classifiers are used to list catastrophic faults according to their likelihood of occurrence. The methodology is demonstrated on both simulation and high-volume manufacturing data showing excellent overall diagnosis rate.

Test cost reduction for RF devices has been an ongoing topic of interest to the semiconductor manufacturing industry. Automated test equipment designed to collect parametric measurements, particularly at high frequencies, can be very costly. Together with lengthy set up and test times for certain measurements, these cause amortized test cost to comprise a high percentage of the total cost of manufacturing semiconductor devices. In this work, we investigate a spatial correlation modeling approach using Gaussian process models to enable extrapolation of performances via sparse sampling of probe test data. The proposed method performs an order of magnitude better than existing spatial sampling methods, while requiring an order of magnitude less time to construct the prediction models. The proposed methodology is validated on manufacturing data using 57 probe test measurements across more than 3,000 wafers. By explicitly applying probe tests to only 1% of the die on each wafer, we are able to predict probe test outcomes for the remaining die within 2% of their true values.

In the course of semiconductor manufacturing, various e-test measurements (also known as inline or kerf measurements) are collected to monitor the health-of-line and to make wafer scrap decisions preceding final test. These measurements are typically sampled spatially across the surface of the wafer from between-die scribe line sites, and include a variety of measurements that characterize the wafer's position in the process distribution. However, these measurements are often only used for wafer-level characterization by process and test teams, as the sampling can be quite sparse across the surface of the wafer. In this work, we introduce a novel methodology for extrapolating sparsely sampled e-test measurements to every die location on a wafer using Gaussian process models. Moreover, we introduce radial variation modeling to address variation along the wafer center-to-edge radius. The proposed methodology permits process and test engineers to examine e-test measurement outcomes at the die level, and makes no assumptions about wafer-to-wafer similarity or stationarity of process statistics over time. Using high volume manufacturing (HVM) data from industry, we demonstrate highly accurate cross-wafer spatial predictions of e-test measurements on more than 8,000 wafers.

This paper discusses a Bayesian fault diagnosis scheme for RF circuits. We use non-idealized spot defect models by taking into account both their resistive and capacitive behavior at the layout level. The likelihoods in the Bayes rule are estimated using nonparametric kernel density estimation. Our case study is an RF low noise amplifier. The diagnosis decisions and the subsequent defect ambiguity analysis are demonstrated using post-layout simulations.

We discuss a fault diagnosis scheme for analog integrated circuits. Our approach is based on an assemblage of learning machines that are trained beforehand to guide us through diagnosis decisions. The central learning machine is a defect filter that distinguishes failing devices due to gross defects (hard faults) from failing devices due to excessive parametric deviations (soft faults). Thus, the defect filter is key in developing a unified hard/soft fault diagnosis approach. Two types of diagnosis can be carried out according to the decision of the defect filter: hard faults are diagnosed using a multi-class classifier, whereas soft faults are diagnosed using inverse regression functions. We show how this approach can be used to single out diagnostic scenarios in an RF low noise amplifier (LNA).