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Andrew R. Cherenson

dblp:40/4506 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Processor architecture and microarchitecture · 88% Performance modeling and evaluation · 12%

Topics — the 4 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
instruction set architecture
0.011987
RISCs versus CISCs for Prolog: A Case Study · ASPLOS 1987
Processor architecture and microarchitecture › instruction set architecture › instruction set style
RISC vs CISC
0.011987
RISCs versus CISCs for Prolog: A Case Study · ASPLOS 1987
Performance modeling and evaluation
benchmarking
0.011987
RISCs versus CISCs for Prolog: A Case Study · ASPLOS 1987
Processor architecture and microarchitecture › instruction set architecture
tagged architecture
0.011987
RISCs versus CISCs for Prolog: A Case Study · ASPLOS 1987

Methods — techniques the papers use, named apart from their topics

simulation · 0.0benchmarking · 0.0
YearPublicationVenuePosition
1987 RISCs versus CISCs for Prolog: A Case Study
abstract
This paper compares the performance of executing compiled Prolog code on two different architectures under development at U. C. Berkeley. The first is the PLM, a special-purpose CISC architecture intended as a coprocessor for a host machine. The second is SPUR, a general-purpose RISC architecture that supports tagged data. Fourteen standard benchmark programs were run on both the PLM and SPUR simulators. The compiled code for SPUR was obtained by simple macro-expansion of PLM code generated by the PLM Prolog compiler. The two implementations are compared with regard to static and dynamic program size, execution speed, and memory system performance. On average, the macrocoded SPUR implementation has a static code size 14 times larger than the PLM, executes 16 times more instructions, yet requires only 2.3 times the number of machine cycles (or has the performance of 0.43 PLMs). When memory system performance is taken into account, SPUR is equivalent to 0.29 PLMs. Optimizations of the macro-expanded code and minor architectural changes to SPUR would increase this ratio to 0.53, or 0.60 for the largest benchmarks. Thus a tagged RISC architecture can execute Prolog at least half as fast as a special-purpose CISC architecture for Prolog.
Gaetano Borriello, Andrew R. Cherenson, Peter B. Danzig, Michael N. Nelson
ASPLOS2