Demo Data from EDBT 2026 / reviewers in the wild / expert
R. M. M. Oberman
dblp:40/4557
· DBLP profile ↗
4ranked-venue papers
4as first author
0since 2021 · last 1980
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 4 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
4 papers |
Integrated circuit design · 48% Electronic design automation · 36% Processor architecture and microarchitecture · 16% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.0 | 3 | 1980 | The J-K Gate · IEEE Trans. Computers 1976 A Flexible Rate Multiplier Circuit with Uniform Pulse Distribution Outputs · IEEE Trans. Computers 1972 Comments on "Modular Replacement of Combinational Switching Networks" · IEEE Trans. Computers 1980 |
Electronic design automation
logic synthesis |
0.0 | 1 | 1980 | Comments on "Modular Replacement of Combinational Switching Networks" · IEEE Trans. Computers 1980 |
Processor architecture and microarchitecture › arithmetic unit
arithmetic logic unit |
0.0 | 1 | 1976 | The J-K Gate · IEEE Trans. Computers 1976 |
Processor architecture and microarchitecture
computer arithmetic |
0.0 | 1 | 1974 | A New Explanation of the Reflected Binary Code · IEEE Trans. Computers 1974 |
Integrated circuit design › digital circuit design
pulse generation |
0.0 | 1 | 1972 | A Flexible Rate Multiplier Circuit with Uniform Pulse Distribution Outputs · IEEE Trans. Computers 1972 |
Processor architecture and microarchitecture › computer arithmetic
signed digit representation |
0.0 | 1 | 1974 | A New Explanation of the Reflected Binary Code · IEEE Trans. Computers 1974 |
Methods — techniques the papers use, named apart from their topics
modular replacement · 0.0computer-aided design · 0.0uniform pulse distribution · 0.0serial conversion · 0.0programmable numerator and denominator · 0.0programmable gate · 0.0parity check · 0.0TTL integrated circuits · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1980 | Comments on "Modular Replacement of Combinational Switching Networks"abstractThe result of the "modular replacement of combinational switching networks method" by Schmidt and Metze1is discussed in this correspondence. It shows that the switching function of the last example used to demonstrate the power of the developed computer programs, can be implemented in "library modules" at less than half the cost of the best computer result. With other "non- library" modules being ordinary integrated circuits, an even better result can be obtained. R. M. M. Oberman |
IEEE Trans. Computers | 1 |
| 1976 | The J-K GateabstractFor many years two-input NAND, AND, NOR, OR and EX-OR gates have been commercially available as cheap quad TTL integrated circuits (IC's). Ideas on quad programmable two-input gates (three inputs per gate) have been published in the literature but have not reached the commercial stage [1]. However, complicated and expensive arithmetic logic units (ALU's) programmable to perform 16 different functions on two 4-bit arguments have become commercially available. The four sections of ALU's are not individually programmable. R. M. M. Oberman |
IEEE Trans. Computers | 1 |
| 1974 | A New Explanation of the Reflected Binary CodeabstractReflected binary (RB) code words plus an even parity check can be considered as signed digit (SD) representations of the corresponding natural binary (NB) code words. The SD code words allow a simple serial conversion with the least significant bit leading of their digits forming the RB code words into the NB code words. R. M. M. Oberman |
IEEE Trans. Computers | 1 |
| 1972 | A Flexible Rate Multiplier Circuit with Uniform Pulse Distribution OutputsabstractIn digital integrated circuits (IC's) a synchronous binary-rate multiplier is commercially available, generating a programmable number of output pulses during each internal counting cycle having a length equal to a power of two. These output pulses are not equally divided over that fixed internal counting cycle and the generated binary rate has a fixed denominator. In this note a new type of binary-rate multiplier is described. This circuit allows the programming of both numerator a and denominator b of the rate of the numbers of output and input pulses. It operates in such a way that during a cycle of b pulses the circuit output generates a number of pulses divided over the cycle of b pulses as equally divided as is possible in digital systems. R. M. M. Oberman |
IEEE Trans. Computers | 1 |