Demo Data from EDBT 2026 / reviewers in the wild / expert
Hiroyuki Sugiyama
dblp:40/468
· DBLP profile ↗
4ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 50% Interconnection networks and networks-on-chip · 50% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Interconnection networks and networks-on-chip › error control
error detection and recovery |
0.0 | 1 | 2003 | A 1.3GHz fifth generation SPARC64 microprocessor · DAC 2003 |
Processor architecture and microarchitecture
microprocessor design |
0.0 | 1 | 2003 | A 1.3GHz fifth generation SPARC64 microprocessor · DAC 2003 |
Methods — techniques the papers use, named apart from their topics
error detection and recovery · 0.0SOI CMOS · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | Design Methodology for 2.4GHz Dual-Core MicroprocessorabstractThis paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64trade microprocessor with 90nm CMOS technology. It focuses on the newly adopted techniques, such as efficient data management in dual-core design, fast delay calculation of the noise-immune clock distribution circuit, enhanced signal integrity analysis of a large-scale custom macro design, and enhanced diagnosis capability using a logic BIST circuit. Noriyuki Ito, Hiroaki Komatsu, Akira Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, Hiroyuki Sugiyama, Ryoichi Yamashita, Ken-ichi Nabeya, Hironobu Yoshino, Hitoshi Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda |
ASP-DAC | 6 |
| 2006 | Diagonal routing in high performance microprocessor designabstractThis paper presents a diagonal routing method which is applied to an actual microprocessor prototype chip. While including the layout functions for the conventional Manhattan routing with horizontal and vertical directions, a new diagonal routing capability is added as one of the routing functions. With this enhancement, diagonal routing becomes an additional strategy for improving delays of critical paths in the microprocessor design. This method was applied to the prototype chip of the Fujitsu SPARC64 microprocessor with two CPU cores using 90nm process technology. By applying the diagonal routing to long distance nets, net length is reduced by 36% per net on average. When the diagonal routing is applied to a critical path, path delay is improved by as much as about 14 pico-seconds per net on a path. This improvement is more than the delay of a gate with no load. This prototype chip proved that or method was effective in reducing the total net length and improving path delays Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita, Hiroshi Ikeda, Hiroyuki Sugiyama, Hiroaki Komatsu, Yoshiyasu Tanamura, Akihiro Yoshitake, Kazuhiro Nonomura, Kinya Ishizaka, Hiroaki Adachi, Yutaka Mori, Yutaka Isoda, Yaroku Sugiyama |
ASP-DAC | 5 |
| 2003 | A 1.3GHz fifth generation SPARC64 microprocessorabstractA 5th generation SPARC64 processor is fabricated in 130nm SOI CMOS process with 8 layers of Cu metallization. It runs at 1.3GHz with 34.7W power dissipation in the laboratory. The chip contains over 190M transistors with 19M in logic circuits. The chip size is 18.14mm x 15.99mm. The error detection and recovery mechanism is implemented for execution units and data path logic circuits in addition to on-chip arrays to detect and recover from data logic error. This processor is developed by using mostly in-house CAD tools. Hisashige Ando, Yuuji Yoshida, Aiichiro Inoue, Itsumi Sugiyama, Takeo Asakawa, Kuniki Morita, Toshiyuki Muta, Tsuyoshi Motokurumada, Seishi Okada, Hideo Yamashita, Yoshihiko Satsukawa, Akihiko Konmoto, Ryouichi Yamashita, Hiroyuki Sugiyama |
DAC | 14 |
| 2003 | A Physical Design Methodology for 1.3GHz SPARC64 MicroprocessorabstractWe present a physical design methodology that was applied to the design of Fujitsu 1.3 GHz SPARC 64 microprocessor. A tool-set called GigaGate was developed based on this methodology. The goal of GigaGate is to support the design team to complete the high-performance microprocessor design on schedule. Noriyuki Ito, Hiroaki Komatsu, Yoshiyasu Tanamura, Ryoichi Yamashita, Hiroyuki Sugiyama, Yaroku Sugiyama, Hirofumi Hamamura |
ICCD | 5 |