A digital camera sensor will incur pixel defects both in fabrication and during its lifetime. While manufacturing defects are corrected in the factory, in-field defects are prohibitively expensive to fix, and can eventually affect the picture quality. During the last 10 years, we have conducted a study of defect development in digital imagers, in which we had access to about 40 cameras and a database of past photos taken by them. The data we collected allows us to quantify characteristics of defect growth. Our investigations have shown that pixel defects are permanent, and their number grows with time. We found that the main type of defect is hot pixels, which are pixels that appear as a bright spot in the image even without any illumination. We also observed that the defects are distributed randomly over the sensor area and are not clustered. By studying past pictures of each given camera we found that the defect growth rate is constant over time. These spatial and temporal characteristics led us to the conclusion that defects are not likely related to material degradation or imperfect fabrication, but are caused by environmental stress such as cosmic rays radiation. Measuring the effect on the defect rate of sensor parameters such as sensor area, number of pixels, pixel size, and sensor technology (CCD - Charge Coupled Device vs. APS - Active Pixel Sensor) yielded a power law, implying that increasing the number of pixels by shrinking the pixel size will result in a higher defect rate and is, therefore, not recommended.

Modern FPGAs are large enough to implement multi-processor systems-on-chip (MPSoCs). Commercial FPGA companies also provide system design tools that abstract sufficient low-level system details to allow non-FPGA experts to design these systems for new applications. The application presented herein was designed by photomask researchers to implement a new technique for measuring the transparency of bimetallic grayscale masks using an FPGA platform. Production of the bimetallic grayscale masks requires a direct-write laser system. Previously, system calibration was determined by writing large rectangles of varying transparency on a mask and then measuring them using a spectrometer. The proposed technique uses the same mask-writing system but adds photodiode sensors connected to a multiprocessor computing system implemented on an FPGA. The added sensors combined with the laser beam's smaller focal point allows the calibration rectangles to be up to 5000 times smaller than those required by the spectrometer. This allows for direct mask verification on a mum-sized scale. Furthermore, the MPSoC design on the FPGA is easily scalable to support an increased number of photodiodes for the future addition of a feedback approach to the project.

A 3D heterogeneous sensor using a stacked chip has recently been proposed. While the sensors are located on one of the planes, the other planes provide for analog processing, digital signal processing, and wireless communication. This paper focuses on its DSP plane, in particular on the implementation of the ICA (independent component analysis) algorithm in the DSP plane. ICA is a recently proposed method for solving the blind source separation problem. The objective is to recover the unobserved source signals from the observed mixtures without the knowledge of the mixing coefficients. We present a parallel architecture utilizing the reconfigurable J-platform, which employs coarse-gain VLSI cells. These include a universal nonlinear (UNL) cell, an extended multiply accumulate (MA PLUS) cell, and a data-fabric (DF) cell. The coarse-grain approach has the distinct advantages of reduced external interconnect, much reduced design time, and manageable testability. Additionally, the other algorithms needed for the 3D HSoC can also be mapped on to the same resources, by time multiplexing, thereby reducing the silicon area needed.

The complexity and speed of monolithic FPGA based custom computers has been set by the presence of defective sections which limit chip area. Test FPGAs show that laser link defect avoidance routing around flawed blocks generates delays <50% of active switches, making the error cell distribution nearly invisible.

Creating large area FPGA's is limited by the presence of defective sections. The techniques developed in wafer scale work solve this problem by using defect avoidance routing around flawed blocks to build complete working systems. FPGA's have the main features required for successful defect avoidance systems: a repeatable cell, built in need for switchable flexible routing and high flexibility with potentially large number of applications. Laser formed connections and cuts have proved to be effective in bypassing fabrication time defects and creating defect free working systems up to wafer scale in area. Power shorts and clock distribution errors can effectively be eliminated using these laser links. In addition it is important to minimize signal delays so the bypassing of the defective cells is nearly invisible. Experiments on a small test FPGA shows defect avoidance routing using laser link structures generates delays which are about half those obtained by the active switches required for the FPGA's operation. Thus laser defect avoidance after fabrication removes the errors creating a large area FPGA whose defective cell distribution is nearly unseen by the user.

The circuit design of a large area magnetic field sensor array (LAMSA) is described. This prototype is developed for applications in magnetic field mapping and tactile sensor arrays. To enable the production of such a large sensor system, redundancy schemes are implemented and a laser interconnection post fabrication technique is used for fault repairs. The design restructurable capabilities rely on local redundancy schemes for the sensor grid and global redundancy schemes for the surrounding control circuits. Experimental results obtained on a laser restructurable subarray of magnetic field sensor cells are shown. A study of the robustness of the local sensor grid redundancy schemes is presented.

The implementation of a Hough transform processor using a wafer-scale-integration technology, restructurable VLSI circuit is described. The Hough transform is typically used as a grouping operation in an image processing sequence. The transform discussed here groups pixels in order to extract linear features. This calculation is realized with a wafer-scale processor that allows a complete line extraction system to be integrated on a single PC board. Also discussed is the use of the CAD tools that allowed this processor to be realized without incurring silicon layout and processing overhead.>