In this paper, we present a testability-based method to combine three different DFT techniques: partial reset, partial observation, and partial scan. This approach combines the complementary strengths of the DFT techniques taking advantage of their different cost/benefit trade-offs, and results in more testable circuits with reduced design penalty.

In this paper, we present a new method for selecting flip-flops for partial scan. Our method ranks all flip-flops based on a sensitivity analysis that determines the improvement in the testability of the circuit as a result of scanning a flip-flop. Testability is computed with respect to a given set of target faults. Our method can estimate the number of scan flip-flops needed to reach a good fault coverage.

The authors describe efforts to develop the Q.931 protocol software for the 5ESS Central Office Switch. Q.931 is a layer-3 message-based, user/network interface protocol for the integrated services digital network (ISDN). The approach uses a single formal specification written in the Augmented Protocol Specification Language to model the 1.931 protocol as a set of communicating extended finite state machines. From this specification, tools validate the protocol and generate the bulk of a C language implementation. The authors successfully integrated this code, along with other handwritten code, into a working system in the lab. Their results demonstrate that protocol tools can be used effectively to develop high quality protocol software quickly from formal specifications.>

Partial reset is an inexpensive design for test technique in which an additional primary input is connected to the reset or the set inputs of a subset of flip-flops (FFs). In this paper, we present a new method to select the FFs to be initialized and their initial values. The FFs are selected based on their contribution to the testability of the circuit. A sensitivity analysis is done to determine the ranking of FFs. The results obtained by the new method show that our selection of FFs gives consistently better fault coverage than the previously used one.>

In this gaper we show that even when a sequential test generator does a perfect job and achieves 100% detectable fault coverage, a circuit passing the test may still exhibit severe testability problems caused by undetectable faults that prevent initialization (FPIs). Thus 100% fault coverage may be a misleading quality indicator, unless undetectable FPIs are accounted for. We present the first algorithm able to identify undetectable FPIs and we report the results obtained for the sequential benchmark circuits. We also discuss the design for testability techniques that make these faults detectable.